Seong-Woon Choi

Block copolymer multiple patterning integrated with conventional ArF lithography

We present block copolymer multiple patterning as an efficient and truly scalable nanolithography for sub-20 nm scale patterning, synergistically integrated with conventional ArF lithography. The directed assembly of block copolymers on chemically patterned substrates prepared by ArF lithography generated linear vertical cylinder arrays with a 20 to 30 nm diameter, enhancing the pattern density of the underlying chemical patterns by a factor of two or three. This self-assembled resolution enhancement technique affords a straightforward route to highly ordered sub-20 nm scale features via conventional lithography.

Manufacturability evaluation of model-based OPC masks

A systematic method for the model-based optical proximity correction in presented. This is called optical proximity effect reducing algorithm (OPERA) and has been implemented to TOPO, an in-house program for optical lithography simulations. Comparing simulational results as well as experimental results, we found that OPERA is not only suitable for shape restoration but also for resolution enhancement. However, the resulting optimized patterns have a high degree of complexity and this brought up a number of issues for mask manufacturing. First, data volume and exposure time were dramatically increased for conventional e-beam file formats. This was solved by using the MODE6 format that preserves data hierarchy. Second, due to excessive shot divisions, a variable-shaped beam machine could not finish the exposure process. A raster-scan beam machine successfully finished the exposure. Finally, a die-to-die inspection was performed but many false defects that do not affect wafer printing were defected. This will be solved by a new type of tool that inspects a mask by evaluating its aerial image.

The analysis of EUV mask defects using a wafer defect inspection system

EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still critical challenges for EUVL to address to become a mature technology like todays litho workhorse, ArF immersion. Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the requirement as of today. In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection.

The new test pattern selection method for OPC model calibration, based on the process of clustering in a hybrid space

Model-based Optical Proximity Correction (OPC) is widely used in advanced lithography processes. The OPC model contains an empirical part, which is calibrated by fitting the model with data from test patterns. Therefore, the success of the OPC model strongly relies on a test pattern sampling method. This paper presents a new automatic sampling method for OPC model calibration, using centroid-based clustering in a hybrid space: the direct sum of geometrical sensitivity space and image parameter space. This approach is applied to an example system in order to investigate the minimum size of a sampling set, so that the resulting calibrated model has the error comparable to that of the model built with a larger sampling set. The proposed sampling algorithm is verified for the case of a contact layer of the most recent logic device. Particularly, test patterns with both 1D and 2D geometries are automatically sampled from the layer and then measured at the wafer level. The subsequent model built using this set of test patterns provides high prediction accuracy.

Fabrication of gated nanosize Si-tip arrays for high perveance electron beam applications

Summary form only given. Nanosize Si-tip arrays with gated electrodes have been fabricated using self-aligned method. In order to have parallel electron beam (high perveance beam) toward the anode plate, we have designed a nanosize tip array with heights of the tip slightly less than that of a gate electrode. High perveance beam is supposed to provide a better focusing of electron beams. Hence, it is important to have a high perveance electron beam for nano lithographic application.

Methodology of flare modeling and compensation in EUVL

Flare in EUV mirror optics has been reported to be very high and long range effect due to its character which is inversely proportional to the 4th order of wavelength. The high level of flare will generate CD (Critical Dimension) variation problem in the area where the gradient of aerial pattern density is large while the long range influencing character would confront an issue of computational challenge either for OPC (Optical Proximity Correction) modeling or for any other practical ways to accommodate such a long range effect. There also exists another substantial challenge of measuring and characterizing such a long range flare accurately enough so that the characterized flare can successfully be used for the compensation in the standard OPC flow.

Fabrication of subwavelength-size aperture for a near-field optical probe using various microfabrication procedures

We successfully fabricated subwavelength-size silicon oxide apertures on a cantilever array as a near-field optical probe. Various semiconductor processes were utilized for subwavelength-size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, and isotropic oxide etching was carried out. 2, 3, and 4 μm size dot arrays were initially photolithographically patterned on a Si(100) wafer. After fabrication of a V-groove shape by anisotropic etching, oxide growth at 1000 °C was performed to have an oxide etch mask. The oxide layer on the Si(111) plane has been utilized as an etch mask for plasma dry etching and water-diluted HF wet etching for subwavelength-size aperture fabrication. A Au thin layer was deposited on the fabricated oxide aperture on the cantilever array. After this procedure, the initial opening, 300 nm of the oxide aperture was reduced down to ∼95 nm.

Evaluation of the attenuated PSM performance as the shifter transmittance and illumination systems

Phase shift mask (PSM) with optical proximity effect correction (OPC) is the efficient tool of the resolution enhancement technology (RET). Particularly, it is commonly known that the attenuated PSM(att.PSM) has some merits in the memory device with a repeated cell patterns. But there are only a few results of what illumination systems affect the performance of the attPSM and how much the transmittance of the attPSM affects the lithography performance -- such as resolution and depth of focus. In this paper, we will present the optimized illumination systems for patterning with the attPSM, and the relationship between the transmittance of the attPSM and the lithography performance by using simulations and experiments. The resolution of KrF lithography with the Hi-T att.PSM can be extended to 130 nm through the simulation. We extend the resolution of KrF lithography with the Hi-T att.PSM to 150 nm through the experiment.

The application of EUV lithography for 40nm node DRAM device and beyond

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography technology for the 32 nm half-pitch node and beyond. We have evaluated the Alpha Demo Tool(ADT) characterizing for mixed-andmatched overlay(MMO), flare noise, and resolution limit. For process integration, one of the important things in EUVL is overlay capability. We performed an overlay matching test of a 1.35NA and 193 immersion tool using a low thermal expansion material(LTEM) mask. We also investigated the flare level of the EUV ADT for device applications. The current EUV tool has a higher flare level than ArF lithography tools. We applied a contact layer for 40nm node device integration to reduce the variation in critical dimension(CD) from the flare noise.

Physical simulation for verification and OPC on full chip level

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.