Seongnam Kwon

PeaCE: A hardware-software codesign environment for multimedia embedded systems

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW cosimulation, but also HW-SW codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The PeaCE codesign environment is the first full-fledged HW-SW codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, PeaCE specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.

A retargetable parallel-programming framework for MPSoC

As more processing elements are integrated in a single chip, embedded software design becomes more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design constraints such as hardware cost, power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, the programmer should manually optimize the parallel code for each target architecture and for the design constraints. Thus, the design-space exploration of MPSoC (multiprocessor systems-on-chip) costs become prohibitively large as software development overhead increases drastically. To solve this problem, we develop a parallel-programming framework based on a novel programming model called common intermediate code (CIC). In a CIC, functional parallelism and data parallelism of application tasks are specified independently of the target architecture and design constraints. Then, the CIC translator translates the CIC into the final parallel code, considering the target architecture and design constraints to make the CIC retargetable. Experiments with preliminary examples, including the H.263 decoder, show that the proposed parallel-programming framework increases the design productivity of MPSoC software significantly.

Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the peace codesign environment mainly targeting for multimedia applications with real-time constraints. Peace specifies the system behavior with a heterogeneous composition of three models of computation. The Peace environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique

Fast design space exploration framework with an efficient performance estimation technique

This work presents the design space exploration framework that consists of two design loops: cosynthesis loop for component selection and mapping of the function blocks to the processing components, and communication DSE loop for communication architecture optimization. Before entering into the cosynthesis loop, it is critical to estimate the performance of junction blocks. We also propose a performance estimation method of software function blocks considering the effect of architecture variation, compiler optimization, and data dependent behavior. It is to run the entire application with code augmentation on the instruction set simulator of the target processor. In the cosynthesis loop, the performance of the entire application is easily computed as a linear combination Of function block performance values. Experimentation with real-life applications proves the viability of the proposed technique.

Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications

Embedded software design for MPSoC needs parallel programming. Popular programming languages such as C and C++ are not adequate for initial specification since they are designed for sequential execution. Therefore models of computations that express concurrency naturally are preferred for initial specification, among which dataflow model has been widely used to specify signal processing applications. While software generation from SDF specification has been researched extensively, data- parallelism has not been properly considered in the previous work. This paper presents data-parallel code generation technique from SDF graphs. We use OpenMP directives to specify data-parallelism and resort OpenMP compiler to obtain the final target code. Preliminary experimentation with real-life examples shows the viability of the proposed technique.

Serialized multitasking code generation from dataflow specification

This paper is concerned about multitasking embedded software development from the system specification to the final implementation including design space exploration(DSE). In the proposed framework, dataflow model is used for task specification. Multitasking software is generated for the performance evaluation of architecture candidates during the DSE process. Since the same code is also used for the final implementation, it is highly desirable to make it portable and efficient. In this paper, we propose a serialized multitasking code generation technique from dataflow specification to run the multitasking application without OS on any target processor. The code serialization also reduces runtime overhead of task switching as previous works have reported. By separating run-time scheduler generation from task code generation, various scheduling policies can be explored. Experiments with DiVX application confirm the viability of the proposed technique.

Serialized parallel code generation framework for MPSoC

The models of computations that express concurrency naturally are preferred for initial specification of MPSoC system, since popular programming languages such as C and C++ are designed for sequential execution. In our previous work, we proposed a design framework where two models are used for the initial specification of the system behavior; task model at the top level and dataflow model inside each task. After the partition and mapping process is performed with each architecture candidate, the target code is automatically generated for both Design-Space Exploration (DSE) and final implementation. In this article, we focus on parallel code generation for MPSoC, proposing two main techniques. The first is to express functional and data parallelism differently following the partition and mapping decision. In the proposed technique, the generated code consists of multiple tasks running concurrently, which achieves functional parallelism. On the other hand, we use OpenMP directives to express data parallelism inside a task. Second is to adopt the code serialization technique to execute a multitasking application without OS scheduler, aiming to generate the highly portable code on various platforms for an efficient DSE process. We extend the previous code serialization techniques to multiprocessor systems and utilize the formal properties of the dataflow model for efficient code generation. The experiments including H.263 codec example show the viability of the proposed technique and the efficiency of the generated code.