Seppo Pienimaa

Thin polyaniline films in EMI shielding

Abstract Electromagnetic interference shielding efficiency has been measured for highly electrically conducting Polyaniline-Camphor Sulfonic Acid. The polymer is spin coated from m-cresol solution on an electrically insulating substrate as a 1–30 μm thick layer having a conductivity of 10–100 S/cm. The shielding efficiencies (SE) for these electrically thin polyaniline films have been measured in the near-field with a dual-chamber box and in the far-field with a transmission line method in the frequency range 0.1–1000 MHz. The measurements show that SE depends primarily on the surface resistance both in the far-field and the near-field. An additional effect >10 dB is seen when the two layer structure is measured in the near field. By using layer structures, the SE is >40 dB up to ca. 100 MHz in the near-field and 39 dB at 1 GHz in the far-field.

Evaluation of Inkjet Technology for Electronic Packaging and System Integration

The main trend of the electronic packaging industry has been on increasing the packaging density and increasing the functionality, but now also the interest on flexible manufacturing has grown. In this paper, we discuss the utilization of the inkjet technology for the electronic packaging and system integration. Inkjet technology provides fully-additive non-contacting deposition method that is suitable for flexible production. In this paper, we demonstrate the capability of the inkjet technology for the printable electronics through a highly-integrated RF SiP application, which is manufactured partly by inkjet printing. The SiP contains discrete components and an ASIC with a minimum pitch of 136 mum and the size of pads is 65 mum. The width of lines/spaces is designed with a rule of 75 mum/75 mum, but also narrower lines can be printed. The width of lines depends on the properties of surface, ink, and drop volume. The properties of the surface can be manipulated with proper surface treatment. In this paper, almost 20% decrease in a diameter of drop is reported when the surface treatment is used.

Stacked modular package

This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.

High-density packaging for mobile terminals

Personal electronics devices are miniaturized to be more comfortable to carry. This size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Mobile terminal electronics have set a challenge for packaging and provided the motivation to verify emerging technologies. Chip scale packages (CSP), flip-chip, and passive integration technologies have been verified by building two technology verifiers, both GSM mobile terminals based on the electronics of existing products. High-density PWB (HDPWB) technologies were selected to provide the required routing density for flip-chip assembly. These electronics modules were assembled into the mechanics of existing mobile terminals, facilitating full electrical characterization. The digital part of the mobile terminal is characterized by large ICs including memories, data processors, and many discrete components with equal values for interfacing, filtering, and timing. The principle aims in packaging the digital part were to reduce the number of discrete passives by the use of silicon based flip-chip integrated passive devices (IPD) and to eliminate single-chip packaging, where appropriate. The most significant improvement in the density of the digital part was achieved with the use of CSPs in Verifier 1 and flip-chip integrated circuits (ICs) and IPDs in Verifier 2, both requiring HDPWBs. Existing IC designs were converted from wire bonded to flip-chip for the Verifier 2. An area reduction approaching 50%, together with significant component and solder joint count reduction was achieved. The radio part is characterized by a few, small ICs and many disparate discrete components used for filtering, matching, timing, etc. The approach used in repackaging the radio part must be different to the digital part case, primarily because any small change to the signal paths can have dramatic effects on the operation of the radio circuits. The most significant radio part achievements were the creation and verification of the MCM-D/Si module in Verifier 1, the conversion to flip-chip of the RFIC in Verifier 2 and the use of IPDs. The areas occupied by the radio part components were reduced, as was the component count and the number of solder joints.

Lithographic patterning of conductive polyaniline

Abstract Electrically conducting patterns of polyaniline are made by utilizing conventional semiconductor industry process. First polyaniline is spin- or spray-coated on an insulating substrate and has a conductivity of 1–100 S/cm. After that UV resist is spread on top of polyaniline, exposed by UV light, developed and removed. As a result one has a patterned polyaniline layer in insulating and in conducting form on top of the substrate. The conductivity remains essentially unaffected below the resist throughout the process and polyaniline turns insulating at places where the resist is removed. The difference between the electrically conducting part and the electrically insulating part is upto 10 10 . When the linewidth is smaller than 100 μm the square resistance increases slightly, because the deprotonating liquid penetrates somewhat below the resist. Linewidths down to 10 μm have been demonstrated. The process has been utilized in making all-polymer circuit boards having resistors and capacitors made of polyaniline.

High density packaging for mobile terminals

Personal electronics devices are miniaturized to be more comfortable to carry. This size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Mobile terminal electronics have set a challenge for packaging and provided the motivation to verify emerging technologies. Chip scale packages (CSP), flip-chip, and passive integration technologies have been verified by building two technology verifiers, both GSM mobile terminals based on the electronics of existing products. High-density PWB (HDPWB) technologies were selected to provide the required routing density for flip-chip assembly. These electronics modules were assembled into the mechanics of existing mobile terminals, facilitating full electrical characterization. The digital part of the mobile terminal is characterized by large ICs including memories, data processors, and many discrete components with equal values for interfacing, filtering, and timing. The principle aims in packaging the digital part were to reduce the number of discrete passives by the use of silicon based flip-chip integrated passive devices (IPD) and to eliminate single-chip packaging, where appropriate. The most significant improvement in the density of the digital part was achieved with the use of CSPs in Verifier 1 and flip-chip integrated circuits (ICs) and IPDs in Verifier 2, both requiring HDPWBs. Existing IC designs were converted from wire bonded to flip-chip for the Verifier 2. An area reduction approaching 50%, together with significant component and solder joint count reduction was achieved. The radio part is characterized by a few, small ICs and many disparate discrete components used for filtering, matching, timing, etc. The approach used in repackaging the radio part must be different to the digital part case, primarily because any small change to the signal paths can have dramatic effects on the operation of the radio circuits. The most significant radio part achievements were the creation and verification of the MCM-D/Si module in Verifier 1, the conversion to flip-chip of the RFIC in Verifier 2 and the use of IPDs. The areas occupied by the radio part components were reduced, as was the component count and the number of solder joints.Personal electronics devices are miniaturized to be more comfortable to carry, this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Mobile terminal electronics have set a challenge for packaging and provided the motivation to verify emerging technologies. Chip Scale Packages (CSP), flip-chip and passive integration technologies have been verified by building two technology verifiers, both GSM mobile terminals based on the electronics of existing products. High Density PWB (HDPWB) technologies were selected to provide the required routing density for flip-chip assembly. These electronics modules were assembled into the mechanics of existing mobile terminals, facilitating full electrical characterization.

Impedance Spectroscopy of the Polymer Thick Film Resistor/Conductor Interface

Impedance spectroscopy has been used to study the electric properties of screen—printed polymer thick film (PTF) resistors over the frequency range 10 Hz — 500 MHz. With a suitable test pattern it was possible to separate the impedance response of the resistor/conductor interface from that of the resistive element itself. This proved to be useful when analysing, whether the manufacturing parameters have more influence on the properties of the interface or the bulk resistor. The main varied manufacturing parameters were curing method, curing temperature and the resistor/conductor interface (pure copper vs. silver treated copper). Furthermore, the test components were kept for 600 hours in a humid environment (85oC / 85% RH), and after this the impedance measurements were repeated. Analysis of the effects of these manufacturing and environmental conditions on the electrical properties of PTF resistors are presented.