Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Sergio Sáez is active.

Publication


Featured researches published by Sergio Sáez.


euromicro conference on real-time systems | 1998

Using exact feasibility tests for allocating real-time tasks in multiprocessor systems

Sergio Sáez; Joan Vila; Alfons Crespo

The paper introduces improvements in partitioning schemes for multiprocessor real time systems which allow higher processor utilization and enhanced schedulability by using exact feasibility tests to evaluate the schedulability limit of a processor. The paper analyzes how to combine these tests with existing bin packing algorithms for processor allocation and provides new variants which are exhaustively evaluated using two assumptions: variable and fixed number of processors. The problem of evaluating these algorithms is complex, since metrics are usually based on comparing the performance of a given algorithm to an optimal one, but determining optimals is often NP hard on multiprocessors. This problem has been overcome by defining lower or upper bounds on the performance of an optimal algorithm and then defining metrics with respect these bounds. The evaluation has shown that the algorithms exhibit extremely good behavior and they can be considered very close to the maximum achievable utilization. It is also shown that dynamic priority policies produce significantly better results than fixed priority policies when task sets require high processor utilizations.


international conference on embedded software and systems | 2005

On using locking caches in embedded real-time systems

A. Martí Campoy; E. Tamura; Sergio Sáez; Francisco Rodríguez; J. V. Busquets-Mataix

Cache memories are crucial to obtain high performance on contemporary processors. However, they have been traditionally avoided in embedded real-time systems due to their lack of determinism. Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. This work reviews several techniques developed by the authors to use cache memories in “real” embedded real-time systems, with the ease of use in mind. Those techniques are based on a locking cache, which offers a very predictable behaviour. Both static and dynamic use are proposed as well as the algorithms and methods required to make the schedulability analysis using two different scheduling policies. Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. Finally, a set of statistical analyses compares the locking cache versus a conventional one.


international conference on reliable software technologies | 2010

Preliminary multiprocessor support of ada 2012 in GNU/Linux systems

Sergio Sáez; Alfons Crespo

The next release of the Ada language, Ada 2012, will incorporate several new features that address current and future software and hardware issues. One of these features is expected to be explicit support for multiprocessor execution platforms. This work reviews the enhancements at the language level required to support real-time scheduling over symmetric multiprocessor platforms, and the corresponding support at the operating system level. It analyses the preliminary support for these features within the Linux kernel and proposes a set of language extensions that will provide the required functionalities. Multiprocessor implementation aspects of other Ada language constructs such as timing events, execution time clocks and interrupt management are also analysed.


international conference on reliable software technologies | 2016

Combining Time-Triggered Plans with Priority Scheduled Task Sets

Jorge Real; Sergio Sáez; Alfons Crespo

Time-triggered and concurrent priority-based scheduling are the two major approaches in use for real-time and embedded systems. Both approaches have their own advantages and drawbacks. On the one hand, priority-based systems facilitate separation of concerns between functional and timing requirements by relying on an underlying real-time operating system that takes all scheduling decisions at run time. But this is at the cost of indeterminism in the exact timing pattern of execution of activities, namely variable release jitter. On the other hand, time-triggered schedules are more intricate to design since all scheduling decisions must be taken beforehand in the design phase, but their advantage is determinism and more chances for minimisation of release jitter. In this paper we propose a software architecture that enables the combined and controlled execution of time-triggered plans and priority-scheduled tasks. We also describe the implementation of an Ada library supporting it. Our aim is to take advantage of the best of both approaches by providing jitter-controlled execution of time-triggered tasks e.g., control tasks, coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements.


international conference on reliable software technologies | 2012

An integrated framework for multiprocessor, multimoded real-time applications

Sergio Sáez; Jorge Real; Alfons Crespo

In this paper we propose an approach for building real-time systems under a combination of requirements: specification and handling of operating modes and mode changes; implementation on top of a multiprocessor platform; integration of both aspects within a common framework; and connection with schedulability analysis procedures. The proposed approach uses finite state machines to describe operating modes and transitions, and a framework of real-time utilities that implements the required behaviour in Ada 2012. Automatic code generation plays an important role: the system is derived from the functional and timing specification, and implemented according to the abstractions provided by the framework. Response time analysis enables assessing the schedulability of the different operating modes and the transitions between modes.


distributed multimedia systems | 2002

Optimal Traffic Shaping with Deterministic Guarantees Using GPS Scheduling

Enrique Hernández-Orallo; Joan Vila i Carbó; Sergio Sáez; Silvia Terrasa

The transmission of video over a high-speed network implies guaranteeing a Quality of Service (QoS). This transmission requires a very demanding reservation of network resources, so optimisation becomes a key issue. Traffic shaping has been proposed as a means for improving network utilisation. This paper introduces a fast and bounded method to obtain the leaky bucket shaper parameters that optimises network reservations (bandwidth and buffers) with deterministic guarantees using GPS scheduling. The algorithm presented finds the optimal solution in 5 or 6 iterations. Another important contribution of this paper is comparing this new admission scheme with different EDF control admission tests. Results show that although GPS is a little less efficient than the optimal EDF scheduler for one node (as expected), it is as efficient as the best RC-EDF known policies for several nodes, or even better when the number of network hops is high.


IFAC Proceedings Volumes | 1998

The Real-Time Stealer 1

Sergio Sáez; A. Garcia; Joan Vila; Alfons Crespo

Abstract Slack stealing algorithms are a widely accepted solution for jointly scheduling both hard deadline periodic tasks and soft aperiodic tasks in real-time computations, and they all imply long searches in real-time computations looking for slack gaps. That makes them impractical to implement in software, specially in the dynamic case, since the scheduler overhead would be very important. The advocated solution is to implement them in hardware, but hardware implementations are not straightforward and they often require an algorithm redesign and to face other important design trade-offs to meet time requirements. This paper presents a complete hardware implementation of a dynamic slack stealing algorithm based on a novel algorithm for slack detection that specially fits in a hardware implementation and introduces improvements in response times over previous ones. The algorithm has been implemented in VHDL and built using a FPGA.


euromicro conference on real-time systems | 1996

A dynamic real-time scheduler for shared memory multiprocessors

Sergio Sáez; Joan Vila; Alfons Crespo

This paper presents a dynamic scheduling algorithm for multiprocessor systems which is guarantee-oriented. The algorithm is based on dynamic priority policy where priorities are inversely proportional to the latest start time (LST) of tasks. The paper includes a comparative study of the algorithm with other two well known dynamic algorithms: the earliest deadline first (EDF) and the least laxity first (LLF). The results show that LST is able to schedule some loads where EDF fails and reduces significantly the number of context switches with respect to LLF. The algorithm has been implemented and tested on a tool for multiprocessor analysis and simulation which is also presented in this paper.


ACM Sigada Ada Letters | 2016

Combined Scheduling of Time-Triggered Plans and Priority Scheduled Task Sets

Jorge Real; Sergio Sáez; Alfons Crespo

Preemptive, priority-based scheduling on the one hand, and time-triggered scheduling on the other, are the two major techniques in use for development of real-time and embedded software. Both have their advantages and drawbacks with respect to the other, and are commonly adopted in mutual exclusion. In a previous paper, we proposed a software architecture that enables the combined and controlled execution of time-triggered plans and priority-scheduled tasks. The goal was to take advantage of the best of both approaches by providing deterministic, jitter-controlled execution of time-triggered tasks (e.g., control tasks), coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements. In this paper, we briey describe the approach, in which the time-triggered plan is executed at the highest priority level, controlled by scheduling decisions taken only at particular points in time, signalled by recurrent timing events. The rest of priority levels are used by a set of concurrent tasks scheduled by static or dynamic priorities. We also discuss several open issues such as schedulability analysis, use of the approach in multiprocessor architectures, usability in mixed-criticality systems and needed changes to make this approach Ravenscar compliant.Preemptive, priority-based scheduling on the one hand, and time-triggered scheduling on the other, are the two major techniques in use for development of real-time and embedded software. Both have their advantages and drawbacks with respect to the other, and are commonly adopted in mutual exclusion. In a previous paper, we proposed a software architecture that enables the combined and controlled execution of time-triggered plans and priority-scheduled tasks. The goal was to take advantage of the best of both approaches by providing deterministic, jitter-controlled execution of time-triggered tasks (e.g., control tasks), coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements. In this paper, we briey describe the approach, in which the time-triggered plan is executed at the highest priority level, controlled by scheduling decisions taken only at particular points in time, signalled by recurrent timing events. The rest of priority levels are used by a set of concurrent tasks scheduled by static or dynamic priorities. We also discuss several open issues such as schedulability analysis, use of the approach in multiprocessor architectures, usability in mixed-criticality systems and needed changes to make this approach Ravenscar compliant.


ACM Sigada Ada Letters | 2015

Implementation of Timing-Event Affinities in Ada/Linux

Sergio Sáez; Jorge Real; Alfons Crespo

Ada 2012 has introduced mechanisms for exploiting multiprocessor platforms at the application level. These include task afinity control and definition of dispatching domains. However, there are other executable entities defined in the language for which there is no such support to afinity control: event handlers. With event handlers we mean both timing-event and interrupt handlers. This paper discusses the consequences of this lack of functionality and explores implementation issues related with this ability. We propose a working implementation for afinity of timing-event handlers on top of Linux.

Collaboration


Dive into the Sergio Sáez's collaboration.

Top Co-Authors

Avatar

Alfons Crespo

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

Joan Vila

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

Jorge Real

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

Silvia Terrasa

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

A. García

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

Joan Vila i Carbó

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

A. Martí Campoy

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

A. Perles

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

J. V. Busquets

Polytechnic University of Valencia

View shared research outputs
Top Co-Authors

Avatar

J. Vila

Polytechnic University of Valencia

View shared research outputs
Researchain Logo
Decentralizing Knowledge