Seung-Ho Jung

Solution-processed zinc-indium-tin oxide thin-film transistors for flat-panel displays

Highly uniform thin-films of zinc-indium-tin oxide (ZITO) semiconductors were formed using solution process with wet-annealing at a low temperature of 250 °C. The solution-processed ZITO thin-film transistors with a top-gate staggered structure were fabricated to exhibit field-effect mobility of 2.04 ± 0.28 cm2/Vs at saturation region, threshold voltage (Vth) of 2.15 ± 0.75 V, subthreshold slope of 0.27 ± 0.14 V/dec. and excellent reliability (ΔVth = −4.35 V) for negative bias temperature illumination stress. Based on the performance, a 10.1 in. full-color liquid crystal display was demonstrated by the optimized full photolithography process.

Near-field fiber tip to handle high input power more than 150 mW

A high-power near-field fiber tip is proposed and demonstrated. This high-power tip can handle an optical power of greater than 150 mW injected into the fiber core, higher than any previous tip. The tip has a unique, thick, heat-conducting metal layer deposited by an electroplating process. The subwavelength aperture of the tip is fabricated by the controlled lapping of the end face with in situ optical monitoring. We also demonstrate using this tip to record on phase change and photoresist media.

Statistical leakage estimation for DRAM circuits

Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical leakage estimation is essential for robust circuit design. Process variations can be monitored by analyzing the test element group (TEG). DRAM has power down mode with ICC2P parameter. To obtain ICC2P current, we need a long circuit-level simulation with an accurate transistor modeling. Therefore, to solve this problem, we need a practical framework which is based on switch-level and standby vector dependent statistical leakage analysis. In this paper, we proposed a TEG based analysis methodology to estimate the leakage current at ICC2P mode. Experiments on DRAM benchmark circuits demonstrate that the estimated results with our methodology are very accurate compared to the measurement data from industrial fabrication.