Seung-yong Cha

Package embedded decoupling capacitor impact on core power delivery network for ARM SoC application

In this paper, a BGA package having a ARM SoC chip is introduced, which has component-type embedded decoupling capacitors (decaps) for good power integrity performance of core power. To evaluate and confirm the impact of embedded decap on core PDN (power distribution network), two different packages were manufactured with and without the embedded decaps. The self impedances of system-level core PDN were simulated in frequency-domain and On-chip DvD (Dynamic Voltage Drop) simulations were performed in time-domain in order to verify the system-level impact of package embedded decap. There was clear improvement of system-level core PDN performance in middle frequency range when package embedded decaps were employed. In conclusion, the overall system-level core PDN for ARM SoC could meet the target impedance in frequency-domain as well as the target On-chip DvD level by having package embedded decaps.

Analysis and verification of board power delivery network impact on DDR3L memory interface in ARM SoC application

In this paper, a DDR3L simulation topology for ARM SoC application is presented and the impact of the board power delivery network (PDN) on a DDR3L memory interface is simulated and analyzed. The analysis of the DDR3L PDN of the package and board will be discussed in the frequency-domain while the DDR power noise and DDR3L data signals are analyzed in the time-domain. A timing jitter comparison of the measured and simulated eye-diagram is presented. Finally, the analysis verifies the importance of including the board PDN to accurately predict the performance of the DDR3L memory interface in the simulation and modeling environment.