Seyoung Oh

Model based cell-array OPC development for productivity improvement in memory device fabrication

Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.

Model-assisted template extraction SRAF application to contact holes patterns in high-end flash memory device fabrication

Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.

Cost effective solution using inverse lithography OPC for DRAM random contact layer

Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics. This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

Process window variation comparison between NTD and PTD for various contact type

As technology node has been shrinking for bit growth, various technologies have been developed for high productivity. Nevertheless, lithography technology is close to its limit. In order to overcome these limits, EUV(Extreme Ultraviolet Lithography) and DSA(Directed Self-Assembly) are being developed, but there still exists problems for mass production. Currently, all lithography technology developments focus on solving the problems related to fine patterning and widening process window. One of the technologies is NTD(Negative Tone Development) which uses inverse development compared to PTD(Positive Tone Development). The exposed area is eliminated by positive developer in PTD, whereas the exposed area is remained in NTD. It is well known that NTD has better characteristics compared to PTD in terms of DOF(Depth of Focus) margin, MEEF(Mask Error Enhancement Factor), and LER(Line End Roughness) for both small contact holes and isolated spaces [1]. Contact hole patterning is especially more difficult than space patterning because of the lower image contrast and smaller process window [2]. Thus, we have focused on the trend of both NTD and PTD contact hole patterns in various environments. We have analyzed optical performance of both NTD and PTD according to size and pitch by SMO(Source Mask Optimization) software. Moreover, the simulation result of NTD process was compared with the NTD wafer level performance and the process window variation of NTD was characterized through both results. This result will be a good guideline to avoid DoF loss when using NTD process for contact layers with various contact types. In this paper, we studied the impact of different sources on various combinations of pattern sizes and pitches while estimating DOF trends aside from source and pattern types.

Mask 3D effects on contact layouts of 1Xnm NAND flash devices

It is a distinctive feature of the metal contact layout in NAND flash memory devices that there are small-pitch contact patterns and random-pitch contact patterns in one layout. This kind of pitch difference between cell array patterns and isolated single patterns hadn’t had a decisive effect on wafers when the illumination condition is not aggressive. However, the pattern pitch difference has caused various problems including the best focus shift due to extreme illuminations. The common DOF margin of a contact layout is degraded when the best focus depth for each pattern is variable. Mask topography effect is well known for the major cause of best focus shift between contact patterns which have different pitches. The demand for device technology node shrink for production cost reduction has required adoption of hyper NA illumination conditions, and this aggressive illumination made it hard to secure an enough common DOF margin due to the best focus shift. In this work, the best focus shift phenomenon among different-pitch patterns caused by mask 3D effects is studied according to the various illumination conditions. It is found that the more aggressive illumination condition is and the bigger the pitch difference among patterns in one layout is, the bigger the best focus shift become. Also, we suggest the solution for avoiding this DOF margin degradation, which is SRAF optimization.

Consideration for application of NTD from OPC and simulation perspective

State of the art Extreme Ultra Violet Lithography (EUVL) gives high hope for further shrinkage of semiconductor devices, but currently, EUVL is not ready for 2xnm node manufacturing and ArF immersion must extend its capability in manufacturing 2xnm devices. Extending the limit of ArF requires varieties of Resolution Enhancement Techniques (RET) such as inverse lithography (ILT) , double patterning (DPT), spacer patterning and so on. One of the brightest candidate for extension of ArF for contact layer is negative tone development (NTD), since this process utilizes the high contrast of the inverse tone of the mask for patterning. NTD usually results in high process margin compared to conventional positive tone development (PTD) process1. Therefore, in this paper we will study application of NTD from optical proximity correction (OPC) and simulation perspective. We will first discuss difference of NTD from PTD. We will also discuss on how to optimize NTD process in simulation perspective, from source optimization to simulation calibration. We will also discuss what to look out for when converting PTD process to NTD process, including OPC models to design rule modification. Finally, we will demonstrate the superiority of NTD process through modeling and simulation results with considering these factors mentioned above.

Novel OPC method to create sub 45nm contact hole using design based metrology

During the past few years, new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as Mask Error Enhancement Factor (MEEF), overlay control, and so on are crucial because large MEEF can make it difficult to satisfy CD target, and bring about large CD variation. Moreover, it can also lead to degraded CD uniformity which would have an undesired influence on device properties. Recently, 2-D random contact hole is getting crucial because it normally has very large MEEF and cause asymmetric proximity effect which can cause large CD variation, and misalignment of layer-to-layer. In other words, the method of optical proximity correction and building accurate OPC model for 2-D random contact hole pattern could be key factor obtaining better CD uniformity with enhanced overlay margin. Furthermore, in order to get very tangible performance, design based metrology system (DBM) is used to evaluate process performance. Design based metrology systems are able to extract information of whole chip CD variation. On top of that, OPC abnormality can be identified and design feedback can be also disclosed. In this paper, we will investigate novel method for sub 45nm 2-D random contact hole printing. First, optical proximity effect (OPE) for two dimensional layout will be investigated. Second, the results of Variable Threshold Modeling (VTM) for various slit contact hole patterns will be analyzed. Third, model based verification will be done and analyzed through full-chip before creating full-chip mask. Finally, sub 45nm 2-D random contact hole printing performance will be presented by DBM.

A study of polymer clad resin with higher modulus for high NA fibers

There has been a rapidly increasing demand for the high numerical aperture (NA) in specialty optical fibers used in recent high power fiber lasers and remote sensing applications. Various polymer clad resins (PCR) have been reported aimed for a low refractive index to achieve a high NA, which resulted in a lower modulus. In this study, we report a novel PCR with a higher modulus whilst maintaining a high NA over 0.44 using newly designed fluorinated oligomer and monomer having low refractive index and high functionality. Some resins prepared various formulations using synthesized oligomers and then compared curing speed.

DFM application on dual tone sub 50nm device

As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the industrys dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have turned there interest to copper process. Widely known, copper process is the trench first damascene process which utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask. Therefore, necessity of DFM[1] for design that meets both dark and clear tone is very large in development of copper process based device. In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask. Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.

Comparative study of chromeless and attenuated phase-shift mask for 0.3-k1 ArF lithography of DRAM

The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.