Sezer Gören

On state reduction of incompletely specified finite state machines

State reduction of incompletely specified finite state machines (ISFSMs) is an important task in optimization of sequential circuit design and known as an NP-complete problem. Removal of redundant states reduces the logic, because of this, chip area decreases. In addition, test generation is easier when the sequential circuit is irredundant. In this paper, we present a heuristic for state reduction of ISFSMs. The proposed heuristic is based on a branch-and-bound search technique and identification of sets of compatible states of a given ISFSM specification. We have obtained results as good as the best exact method in the literature but with significantly better run-times.

Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort

Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is defect-aware even at the crosspoint level. Such logic mapping works with a defect map per each manufactured chip. The problem can be expressed as matching of two bipartite graphs; one for the logic to be implemented and other for the nanocrossbar. This article shows that the problem becomes a Bipartite SubGraph Isomorphism (BSGI) problem within sub-nanocrossbars free of stuck-closed faults. Our heuristic KNS-2DS is an iterative rough canonizer with approximately O(N2) complexity followed by an O(N3) matching algorithm. Canonization brings a partial or full order to graph nodes. It is normally used for solving the regular Graph Isomorphism (GI) problem, while we apply it to BSGI. KNS stands for K-Neighbor Sort and is used for initializing our main contribution 2-Dimensional-Sort (2DS). 2DS operates on the adjacency matrix of a bipartite graph. Radix-2 2DS solves the problem in the absence of stuck-closed faults. With the addition of Radix-3 and our novel Radix-2.5 sort, we solve problems that also have stuck-closed faults. We offer very short runtimes (due to canonization) compared to previous work and have success on all benchmarks. KNS-2DS is also novel from the perspective of BSGI problem as it is based on canonization but not on a search tree with backtracking.

Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration

This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. With the aid of this technique, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Through DPSR, our PUF implementation does not steal real estate from the encrypted design. We also present a new DPSR flow for Xilinx FPGAs, which is difference-based but still allows modular design. It works regardless of the amount of difference between Partial Reconfiguration (PR) modules and is called DPSR-LD, where LD stands for Large-Difference. DPSR-LD is an enabler especially for Spartan-6 FPGA family, as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. Our DPSR-LD also includes a controller that interfaces to the ICAP and can process compressed bitstreams. It is called ICAP+ and occupies only 1% of Spartan-6 slices.

Prediction of cyclosporine A blood levels: an application of the adaptive-network-based fuzzy inference system (ANFIS) in assisting drug therapy.

ObjectiveTherapeutic drug monitoring (TDM) is a procedure in which the levels of drugs are assayed in various body fluids with the aim of individualizing the dose of critical drugs, such as cyclosporine A. Cyclosporine A assays are performed in blood.MethodsWe proposed the use of the Takagi and Sugeno-type “adaptive-network-based fuzzy inference system” (ANFIS) to predict the concentration of cyclosporine A in blood samples taken from renal transplantation patients. We implemented the ANFIS model using TDM data collected from 138 patients and 20 input parameters. Input parameters for the model consisted of concurrent use of drugs, blood levels, sampling time, age, gender, and dosing intervals.ResultsFuzzy modeling produced eight rules. The developed ANFIS model exhibited a root mean square error (RMSE) of 0.045 with respect to the training data and an error of 0.057 with respect to the checking data in the MATLAB environment.ConclusionANFIS can effectively assist physicians in choosing best therapeutic drug dose in the clinical setting.

A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers

Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both value and address of the maximum element within an n-element set of k-bit binary numbers. AB is based on carrying out all of the required comparisons in parallel and then simultaneously computing the address as well as the value of the maximum element. This approach ends up with only one comparator on the critical path, followed by some selection logic. The time complexity of the proposed architecture is O(log2n + log2k) whereas the area complexity is O(n2k). We developed RTL code generators for AB as well as its competitors. These generators are scalable to any value of n and k. We applied a standard-cell based iterative synthesis flow that finds the optimum time constraint through binary search. The synthesis results showed that AB is 1.2-2.1 times (1.6 times on the average) faster than the state-of-the-art.

Reducing compilation time of Zhong's FPGA-based SAT solver

We present schemes to reduce the compilation time of configurable hardware that solves Boolean satisfiability. The SAT solver presented by Zhong et al. (1998) has a large compilation time overhead mainly due to placement and routing of many FPGAs. We attack the problem on three fronts. First, we partition the SAT solver into instance-specific and instance non-specific components. Secondly, we transform SAT instances into canonical forms; and finally we present a board-level multiple-chip architecture to solve large SAT instances. All these efforts amount to a reduction in placement and routing time to configure the configurable hardware. We are able to reduce the compilation time to mere routing time of the implication circuits for each instance of the SAT problem, given the best scenario.

FPGA design security with time division multiplexed PUFs

With the advent of FPGAs, high performance application specific processors can be designed and produced with little investment using a software-like methodology. This ease of design, on the other hand, creates a lot of opportunity for design theft through cloning. A solution to this is bitstream encryption, which is a feature available in rather pricey FPGAs. Physically Unclonable Functions (PUFs) make the same capability possible in ordinary FPGAs. A PUF module provides a signature unique to each chip with the help of manufacturing variations. However, a stable signature requires quite a few bits of PUF, which may not fit in small FPGAs. This paper presents a new PUF based design methodology, which we call Time Division Multiplexed PUF (TDM-PUF). A TDM-PUF divides a single and long PUF into several smaller PUFs run in different time segments. This is made possible by the widely available dynamic partial configuration capability of FPGAs.

Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers

Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different (n, k) cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log n + log k), whereas the fastest in the literature is O(log n log k). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.

Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization

This paper addresses the NP-complete problem of mapping a logic function on to a nanocrossbar with a known defect map. We first show that this problem can be transformed into a Bipartite SubGraph Isomorphism (BSGI) problem. Then we present our proposed KNS-2DS algorithm, which canonizes both graphs in N2 time (N being the number of nodes) and then matches them in N3 time in the worst case. KNS-2DS uses a K-Neighbor Sort (KNS) to initialize our main contribution 2D-Sort (2DS). 2DS is an iterative rough canonizer that lets a straightforward matching algorithm complete the job. Our algorithm offers very short run-times (due to canonization) compared to previous work and has success on all benchmarks. KNS-2DS is also novel from the perspective of the BSGI problem in the sense that it is based on canonization but not on a search tree with backtracking.

Testing finite state machines based on a structural coverage metric

Verification is a critical phase in the development of any hardware and software system. Finite state machines have been widely used to model hardware and software systems. Therefore, testing finite state machines (FSMs) is an important issue. Coverage analysis of a test suite for a systems implementation determines the adequacy and the confidence level of the verification phase. In this paper, we derive a fault coverage metric for a test suite for an FSM specification. We also extend this metric for fault coverage estimation of interconnected FSMs, and we propose symbolic input based fault coverage for large FSMs. Finally, we also study incremental construction of a test suite associated with a coverage for a given FSM specification.