Shahab Shahdoost

Towards a miniaturized brain-machine-spinal cord interface (BMSI) for restoration of function after spinal cord injury.

Nearly 6 million people in the United States are currently living with paralysis in which 23% of the cases are related to spinal cord injury (SCI). Miniaturized closed-loop neural interfaces have the potential for restoring function and mobility lost to debilitating neural injuries such as SCI by leveraging recent advancements in bioelectronics and a better understanding of the processes that underlie functional and anatomical reorganization in an injured nervous system. This paper describes our current progress towards developing a miniaturized brain-machine-spinal cord interface (BMSI) that is envisioned to convert in real time the neural command signals recorded from the brain to electrical stimuli delivered to the spinal cord below the injury level. Specifically, the paper reports on a corticospinal interface integrated circuit (IC) as a core building block for such a BMSI that is capable of low-noise recording of extracellular neural spikes from the cerebral cortex as well as muscle activation using intraspinal microstimulation (ISMS) in a rat with contusion injury to the thoracic spinal cord. The paper further presents results from a neurobiological study conducted in both normal and SCI rats to investigate the effect of various ISMS parameters on movement thresholds in the rat hindlimb. Coupled with proper signal-processing algorithms in the future for the transformation between the cortically recorded data and ISMS parameters, such a BMSI has the potential to facilitate functional recovery after an SCI by re-establishing corticospinal communication channels lost due to the injury.

A multichannel corticospinal interface IC for intracortical spike recording and distinct muscle pattern activation via intraspinal microstimulation

This paper reports on a corticospinal interface IC as a core building block for next-generation integrated neural interfaces targeted at functional recovery from spinal cord injury (SCI). Fabricated in 0.35μm 2P/4M CMOS, the IC integrates a 2-channel, 10b, neural-recording front-end with digitally programmable gain and bandwidth featuring total input noise voltage of 3μVrms and noise efficiency factor (NEF) of 2.47, and a 4-channel, constant-current, stimulating back-end for delivering programmable trains of charge-balanced monophasic or asymmetric biphasic current pulses up to ~100μA. The IC functionality is demonstrated in vivo by low-noise recording of extracellular neural spikes from an anesthetized rats cerebral cortex, and by distinct muscle pattern activation in the rats hindlimb facilitated via intraspinal microstimulation (ISMS).

Cortical control of intraspinal microstimulation: Toward a new approach for restoration of function after spinal cord injury

Approximately 6 million people in the United States are currently living with paralysis in which 23% of the cases are related to spinal cord injury (SCI). Miniaturized closed-loop neural interfaces have the potential for restoring function and mobility lost to debilitating neural injuries such as SCI by leveraging recent advancements in bioelectronics and a better understanding of the processes that underlie functional and anatomical reorganization in an injured nervous system. This paper describes our current progress toward developing a miniaturized brain-machine-spinal cord interface (BMSI) that converts in real time the neural command signals recorded from the cortical motor regions to electrical stimuli delivered to the spinal cord below the injury level. Using a combination of custom integrated circuit (IC) technology for corticospinal interfacing and field-programmable gate array (FPGA)-based technology for embedded signal processing, we demonstrate proof-of-concept of distinct muscle pattern activation via intraspinal microstimulation (ISMS) controlled in real time by intracortical neural spikes in an anesthetized laboratory rat.

An FPGA platform for generation of stimulus triggering based on intracortical spike activity in brain-machine-body interface (BMBI) applications

Brain-machine-body interfaces (BMBIs) aim to create an artificial connection in the nervous system by converting neural activity recorded from one cortical region to electrical stimuli delivered to another cortical region, spinal cord, or muscles in real time. In particular, conditioning-mode BMBIs utilize such activity-dependent stimulation strategies to alter the strength of synaptic efficacy between remote regions of the nervous system and promote functional recovery after injury by exploiting mechanisms underlying neuroplasticity. This paper presents a reconfigurable, field-programmable gate array (FPGA)-based platform that incorporates digital spike discrimination based on user-set thresholding and time-amplitude windowing, as well as decision-making circuitry to generate multichannel stimulation triggers derived from intracortical neural spike activity. The algorithm has been synthesized on a Cyclone II FPGA using Alteras Quartus II design software and validated with prerecorded intracortical neural spike activity from an anesthetized laboratory rat.

A novel design methodology for low-noise and high-gain transimpedance amplifiers

This paper reports on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. Thorough design methodology for high gain and low power TIA design for 2.5 Gb/s optical communication circuits family is presented. A noiseless capacitive feedback is proposed and implemented as a noise efficient feedback network for TIA circuits. Besides, analytical noise calculations in this family of TIA circuits are presented and optimum noise criteria are derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes (PDs) is addressed and a circuit level solution is presented. The measurement results of 0.18 μm chip shows bandwidth of 52 kHz to 1.62 GHz, and transimpedance gain of 75.5 dBΩ while dissipating 26.3 mW from a 2.2 V power supply, including the output buffer. Taking advantage of proposed capacitive feedback network and optimum noise criteria, noise measurement results show average input referred current noise of 3.18 pA/√Hz for this TIA in the bandwidth of operation.

Generation of Stimulus Triggering From Intracortical Spike Activity for Brain–Machine–Body Interfaces (BMBIs)

Brain–machine–body interfaces (BMBIs) aim to create an artificial connection in the nervous system by converting neural activity recorded from one cortical region to electrical stimuli delivered to another cortical region, spinal cord, or muscles in real-time. In particular, conditioning-mode BMBIs utilize such activity-dependent stimulation strategies to induce functional re-organization in the nervous system and promote functional recovery after injury by exploiting mechanisms underlying neuroplasticity. This paper reports on reconfigurable, field-programmable gate array (FPGA)-based implementation of a translation algorithm to extract multichannel stimulus trigger signals from intracortical neural spike activity. The approach features digital spike discrimination based on user-set thresholding and time-amplitude windowing, decision making to support different triggering patterns for various stimulation scenarios, as well as trigger-pattern-dependent blanking schemes for robust operation in the presence of stimulus artifacts. Readily lending itself to low-power, low-area implementation for future integration, the algorithm has been synthesized on a Cyclone II FPGA using Altera’s Quartus II design software and validated experimentally with prerecorded intracortical neural spike activity from an anesthetized laboratory rat.

A miniaturized brain-machine-spinal cord interface (BMSI) for closed-loop intraspinal microstimulation

This paper reports on a fully miniaturized brain-machine-spinal cord interface (BMSI) for closed-loop cortical control of intraspinal microstimulation (ISMS). The system incorporates two identical 4-channel modules, with each module comprising a neural recording front-end, embedded digital signal processing (DSP) unit, and programmable stimulating back-end. The DSP unit is capable of generating multichannel trigger signals for a wide array of ISMS triggering patterns based upon online discrimination of a programmable number of intracortical neural spikes within a pre-specified time bin via thresholding and time-amplitude windowing. The BMSI system is validated experimentally in a rat model of contusion spinal cord injury (SCI) by converting in real-time multichannel neural spikes recorded from the cerebral cortex into electrical stimuli delivered to the lumbar spinal cord below the level of the injury, resulting in distinct patterns of hindlimb muscle activation in the SCI rat.

Delay variation analysis in the presence of power supply noise in nano-scale digital VLSI circuits

In this paper, a novel analytical model is proposed to predict the delay variation due to the power supply noise in nanotechnologies. First, an analytical model is derived for the special case of an inverter gate; next, it is shown that the derived model can also be applied to the other gates. The proposed analytical model helps us to better understand the main contributors to the delay variation and provides an accurate prediction of the delay variation due to the power supply noise in nano-scale VLSI circuits. The accuracy of the proposed model is verified with SPICE simulation in 90nm and 45nm predictive technology models. The maximum error of the proposed model is 7.5% and 8.3% in 90nm and 45nm technologies respectively.