Shahnawaz Farhan Khahro

A Smooth LVRT Control Strategy for Single-Phase Two-Stage Grid-Connected PV Inverters

Based on the inherent relationship between dc-bus voltage and grid feeding active power, two dc-bus voltage regulators with different references are adopted for a grid-connected PV inverter operating in both normal grid voltage mode and low grid voltage mode. In the proposed scheme, an additional dc-bus voltage regulator paralleled with maximum power point tracking controller is used to guarantee the reliability of the low voltage ride-through (LVRT) of the inverter. Unlike conventional LVRT strategies, the proposed strategy does not require detecting grid voltage sag fault in terms of realizing LVRT. Moreover, the developed method does not have switching operations. The proposed technique can also enhance the stability of a power system in case of varying environmental conditions during a low grid voltage period. The operation principle of the presented LVRT control strategy is presented in detail, together with the design guidelines for the key parameters. Finally, a 3 kW prototype is built to validate the feasibility of the proposed LVRT strategy.

Improving Router Efficiency in Network on Chip Triplet-Based Hierarchical Interconnection Network with Shared Buffer Design

In Network on Chip effectiveness of router is dependent on the buffer locality, which makes the efficient flow control. Previous buffer design of Triplet-Based Hierarchical interconnection network (TBHIN) is standard, which leads to insufficient accessibility of this decisive resource, where each virtual channel owns a fixed number of buffers. In this article the design is implemented with sharing the buffers among the virtual channels, to improve the performance. The cyclic queue is allowed the simultaneous access to the shared buffer, which is one of the characteristics of TBHIN. A cycle-accurate simulator is used to obtain packet latency and throughput results for conventional and shared buffer designs. Simulation results illustrate that the packet latency is reduces up to 29% by shared buffer design in comparison to conventional buffer design. Also shared buffer design improves throughput up to 11.87% over the conventional buffer design.

Optimal Pipeline Performance via Transactional Slice with No Branch Prediction Overhead

One of decisive feature in computer system design is the assessment of instruction pipeline. To design it carefully with minimum complexity to achieve enhanced performance and optimum result could be a powerful method. In order to achieve pipeline throughput close to ideal, the penalties of different hazards must be reduced. Branches are also one of those decisive substances that degrade the efficiency and can have dominating effect on the overall performance of CPU pipeline. Transactional Slice (TS) is one of the optimal solutions to tackle this issue, where the last instruction is always branch. Experiments are conducted on SPEC cpu2006 benchmark using Intels pin tool to estimate the size of the transactional slice. Pipeline efficiency is evaluated in this paper in terms of timing and pipelining model. It is observed that the transactional slice mechanism optimizes the efficiency of instruction pipeline.

Simulation for the Control Strategy of Three-Phase Boost-Half-Bridge (BHB) DC-DC Converter with Series Voltage Doubler Rectifiers through Three-Phase High Frequency Transformer

This paper presents simulation for the control strategy of three-phase boost-half-bridge (BHB) DC-DC converter with series voltage doubler rectifiers through three-phase high frequency transformer. The control strategy is consisting of three voltage loops. All the three voltage loops are independent of the input side and controls the input and output power balance from the secondary side of the high frequency transformers only. Moreover, the control strategy has been verified for its appropriate operation by simulating the above said configuration for the same turn ratios as well as for the mismatch turn ratios of high frequency transformers. Finally, the satisfactory simulation results for the proposed control strategy are presented.