Shahrzad Mirkhani

Hierarchical fault simulation using behavioral and gate level hardware models

This paper presents a fault simulation environment that takes advantage of available models at the behavioral and gate levels of abstraction. The simulation takes place in VHDL and for fault simulation, special VHDL models are written that are capable of propagating circuit faults. Behavioral VHDL models propagate fault effects that appear on their input ports; in addition to this, gate level VHDL models are capable of injecting faults on their output lines. The fault simulation environment assumes the existence of the gate level and behavioral models for every component, and uses the appropriate model depending on whether a fault belongs to it or another component. A wrapper simulation model that encloses both models of a component switches automatically between the models. The wrapper takes care of feedback in the sequential circuits by always selecting the gate level of a component for propagating its own faults. This environment fits well with the hardware description language settings in which pre-synthesis behavioral models, post-synthesis gate-level models and a mixed simulation environment are available. The paper shows a mathematical analysis illustrating the performance improvement of this method over the traditional gate-level fault simulation.

Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation

Summary form only given. A new fault simulation method is presented here. The method relies on the simulation cycle timing of event-driven simulators (delta delays in VHDL). This timing is used for propagation of faulty values in faulty sections of a circuit. This method is based on concurrent fault simulation and is implemented in VHDL. VHDL gate models that are capable of propagating faults in fault queues perform this fault simulation. The gate models process their fault queues and propagate them in delta time units. In these models, gates with faulty input values are expanded in delta time to evaluate faulty output values and propagate them to other sections of the circuit. Using ISCAS benchmarks, a performance improvement of up to 500X over serial fault simulation has been obtained. This work is useful for fault simulation of post-synthesis VHDL outputs.

Fault simulation for VHDL based test bench and BIST evaluation

A VHDL based Fault simulation procedure for test bench and test hardware evaluation has been developed. This work is aimed to utilize features of VHDL for more efficient fault simulation. Information about fault detection can be obtained in this environment using fault simulation method and guidelines presented in this report. This environment consists of automated steps, which will lead to fault simulation. Information such as fault coverage, efficiency of test patterns and capability of test hardware to detect faults, can be extracted. Using this environment, one can evaluate test benches and order test vectors or configure BIST (Built-In Self Test) architectures.

RT level reliability enhancement by constructing dynamic TMRS

This paper presents a novel and efficient approach for reliability enhancement at the RT level. The reliability enhancement is performed by utilizing the available resources of a design in their dead intervals. Such resources are used for constructing dynamic TMR structures that can change per clock cycle. In this method all resources participate in constructing TMR structures at least once per a system input to output flow.To evaluate the proposed fault tolerance technique we consider dependability, and area/latency overhead imposed on a circuit by applying our method. In order to evaluate dependability, faults are injected into our test circuits before and after applying our algorithm and fault coverage is measured. Experimental results show that after applying our method, fault coverage is significantly reduced indicating that the reliability of designs is improved.

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

This paper proposes a novel and efficient method for RT level online testing. Our method makes every RT-level resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or latency overhead are due to concurrent operation of active and inactive resources. This method is evaluated by fault simulating several benchmark designs before and after applying the proposed algorithm. Experimental results show that after applying our method, online fault coverage is significantly improved