Shailesh Singh Chouhan

The design and implementation of DTMOS biased all PMOS rectifier for RF energy harvesting

The demand for battery free systems in remote applications raises interest in RF energy harvesting. The front-end for RF energy harvesting is the rectifier circuit that should be capable of operating efficiently at very low RF voltages. The rectifier is a circuit which converts the received RF signal voltage into an output DC voltage. The diode-connected transistor is most commonly employed in realizing the ON-chip rectifier circuit. Usually, the body terminal is connected to the source terminal (BTMOS) in the diode-connected transistor to minimize threshold voltage variation. In this work, we propose the implementation of principle of DTMOS concept where the body terminal is connected to the gate terminal in diode-connected transistor. This implementation facilitates the rectifier with dynamic control over threshold voltage. During forward conduction, the threshold voltage will lower which enables the rectifier to operate at low RF voltage amplitude. Similarly, rise in the threshold voltage during reverse conduction, reduces the reverse conduction loss in the rectifier. The single stage Dickson charge pump based rectifier is designed using BTMOS biasing and DTMOS biasing scheme and have been fabricated with a 0.18 μm standard CMOS process. The performance is expressed in terms of power conversion efficiency(PCE). The measurement results are presented for the targeted resistive load of 1 KΩ and 10 KΩ and RF input power varies from 24dBm to +10dBm at the signal frequency of 433MHz. The measured peak PCE for BTMOS biasing is ≈16% at the input RF power of ≈-8dBm while for DTMOS biasing the peak PCE is ≈23% at the input RF power of ≈-10dBm for the resistive load of 10 kΩ. Thus DTMOS biasing provides ≈7% improvement in PCE with 25% less input RF power.

Efficiency enhanced voltage multiplier circuit for RF energy harvesting

In this work, a simple cascading scheme is proposed for the voltage multiplier (VM) circuit used in RF-energy harvesting. As a result, two switches are eliminated from a traditional two-stage VM circuit. In practice, the traditional two-stage VM circuit is formed by cascading of two standard differential drive rectifiers. The conventional and proposed architectures have been designed and fabricated in a standard 0.18µm CMOS technology. The resistors of values 5k?, 9k?, 30k? and 100k?, respectively, were used to emulate practical load conditions in the measurement. The performance of the circuits was measured in terms of the power conversion efficiency (PCE), and this characterization was done for RF input power ranging from 20dBm to 0dBm. The measured results show that the power conversion efficiency performance at lower input RF power level has been improved in the proposed circuit as compared to the traditional VM circuit. In the best case, the proposed rectifier exhibits the measured maximum power conversion efficiency of 74% at the input RF level of 2dBm for the resistive load of 5k?.

A 0.67-μW 177-ppm/°C All-MOS Current Reference Circuit in a 0.18-μm CMOS Technology

This brief describes a nanopower current reference circuit that has been fabricated in a standard 0.18-μm CMOS technology. The proposed circuit is an extension of the resistorless current reference circuit suggested by Oguey and Aebischer. This extension is a simple circuit arrangement that is capable of reducing the temperature coefficient (TC) of Ogueys circuit. The measurements have been done on ten prototypes in the temperature range of -40 °C to +85 °C. The measured average reference current is 92.2 nA with the average TC value of 177 ppm/°C. The measured average reduction of ≈68% has been achieved in TC value of Ogueys circuit after implementing the proposed arrangement. The operating supply voltage for the proposed circuit ranges from 1.25 to 1.8 V with the line sensitivity of 7.5%/V. The measured maximum average power dissipation of the proposed current reference circuit is 0.67 μW at the supply voltage of 1.8 V.

Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs

In this work a simple all MOS voltage reference circuit has been proposed. To obtain reference output voltage, the thermal compensation has been generated by using a series composite NMOSTs. The voltage reference circuit has been fabricated in a standard 0.18µm CMOS technology. The proposed circuit is capable of working for the supply voltage ranging from 1.25V to 2V. The maximum power dissipation of the proposed circuit is 0.48µW at the supply voltage of 2V. The measurement has been performed over a set of 10 samples. It resulted in the mean temperature coefficient (TC) of 19.302ppm/?C for the temperature range of -40?C to 85?C. The measured mean line sensitivity is 2.217mV/V for the supply voltage ranging from 1.25V to 2V at the room temperature. The measured mean power supply rejection ratio at 10Hz and 1MHz is -55.31dB and -16.67dB respectively for the supply voltage of 1.8V. Moreover, the measured mean noise density without any filtering capacitor at 100Hz and 100kHz are 12.39 µ V / Hz and 0.39 µ V / Hz respectively. Due to its simple circuit implementation, the active area of the circuit is 0.0077mm2.

A modified CMOS nano-power resistor less current reference circuit

In this work, all MOS current reference circuit is proposed using a standard 0.18 μm technology and the simulations were performed using the Cadence Spectre simulator. The proposed current reference circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The Ogueys circuit is capable of generating the reference current in a nanoampere range, but with the high temperature coefficient (TC). The reason for high TC, that we found, is the lack of control over the gate-source voltage of an active resistor used in the design. This gate-source voltage is one of the controlling parameters responsible to obtain adequate thermal compensation for the reference current. In the proposed work, we modified the architecture to limit the variation of the gate-source voltage with the temperature and hence controls the thermal behaviour of the reference current. The working supply voltage of the proposed circuit ranges from 1.25 V to 2 V. The temperature coefficients of the reference current generated from the proposed and conventional architectures are 39.8 ppm/°C and 545.12 ppm/°C respectively at a supply voltage of 1.25V for the temperature ranging from -60°C to 85°C. The maximum power consumption of proposed and conventional architecture is 624.8nW and 468.59nW at a supply voltage of 2 V with the layout area of 0.0013μm2 and 0.001μm2 respectively.

A simple all MOS voltage reference for RFID applications

In recent years Radio Frequency Identification (RFID) systems have become very popular in a number of applications. RFID is an example of mixed signal integrated circuit. Voltage reference is an important circuit for various modules like power generation unit, data converter units of RFID. The basic requirement of reference circuits is a simple architecture with low power consumption and high stability. In this work we are proposing the reference circuit in which output voltage is based on the difference between the gate-source voltages of two NMOS transistors. The proposed voltage reference circuit generates a simulated reference voltage of 610mV with a temperature coefficient of 10.5 ppm/°C for the temperature range of -40°C to 110°C. The maximum power consumption of the proposed circuit is 3μW simulated at a supply voltage of 2V. The line regulation is 0.25mV/V for the supply voltage range from 1.25V to 2V and the PSRR@100Hz is 69 to 75dB. The proposed circuit is implemented using a 180nm standard CMOS technology.

A Low Power Temperature to Frequency Converter for the On-Chip Temperature Measurement

In this paper, we are proposing a simple energy efficient on-chip temperature to frequency converter circuit. The proposed arrangement senses the temperature in terms of the proportional to absolute temperature (PTAT) current. The temperature equivalent PTAT current is then converted into frequency using the source coupled multivibrator circuit. The proposed circuit has been designed and fabricated in a standard 180-nm CMOS technology and occupies silicon area of ≈0.058 mm2. The measurements were performed on ten prototypes. The proposed architecture is capable of working in the temperature range of -40 °C to +85 °C with the supply voltage of 0.9 V ± 10%. The smart temperature sensor achieves a maximum temperature inaccuracy <;±1 °C after applying single point calibration. The average power consumption is ≈600 nW at +85 °C for 0.9 V supply voltage.

Voltage multiplier circuit for UHF RF to DC conversion for RFID applications

The application domain of passive radio frequency identification (RFID) is continuously growing. Hence, the Energy Harvesting has become an attractive approach to ensure that there is sufficient energy available to run the system. In the passive RFID, this energy is harvested by converting the radio frequency (RF) energy into a DC signal received from surrounding. This conversion is performed using a module known as RF-to-DC rectifier. In this work, we are using a high efficiency differential drive CMOS rectifier which is the well established circuit used in RF-to-DC conversion. In order to generate a high DC voltage the cascading of RF to DC rectifier is performed. This arrangement is known as a voltage multiplier (VM). The purpose of this work is to propose a simple and effective method to form the VM arrangement. The proposed VM arrangement is designed in a standard 0.18/μm CMOS technology and simulations are performed using the Cadence spectre simulator. The proposed VM arrangement is implemented in 2, 4, 6 and 8 stages and compared it with Conventional Voltage Multiplier (CVM) with similar stages. We have used a Voltage Conversion Efficiency/Stage (VCES) at the capacitive load of InF and Power Conversion Efficiency (PCE) for a current load of 5μA as a figure of comparison between these two arrangements. It is evident from the simulation that proposed VM arrangement exhibit ≈ 31% raise in VCES, with approximately double PCE as compared to CVM arrangement.

A micro-power 4.8 ppm/°C CMOS voltage reference circuit for linear drop out regulator used in RFID

Low Drop Out (LDO) Regulator is used to maintain steady voltage in power generation blocks. Voltage reference is the most important component in LDO design. The output voltage of LDO is a multiple of the reference voltage. Band gap voltage reference circuits (BVRC) are utilized in LDO for this purpose. The output voltage of a bandgap reference circuit is based on the bandgap voltage of the semiconductor: a well-defined, temperature independent physical value. Diodes and Bipolar Junction Transistors (BJTs) are used for implementing BVRC. In sub-micron CMOS digital processes, lack of lateral pnps can be seen as a disadvantage. In this work, we are proposing a completely MOS based voltage reference scheme. The proposed voltage reference has been implemented using standard 0.18 μm CMOS technology. It generates a constant reference voltage of 594.72mV. The operating supply voltage for the proposed circuit ranges from 1.25V to 2V. The layout area is 0.0055 mm2, with maximum power dissipation of 2.5 μW, simulated at 2V supply voltage. The operating temperature ranges from -10 °C to 110 °C with a temperature coefficient of 4.8 ppm/°C. The simulated line sensitivity is 0.2mV/V, with the supply voltage variation from 1.25V to 2V and the PSRR at 100Hz is -67dB.

A modified cross coupled rectifier based charge pump for energy harvesting using RF to DC conversion

This paper presents a CMOS based RF-to-DC converter using a proposed cross-coupled charge pump for energy harvesting. Extraction of high DC voltages from rectifier block in the charge pumps is always a serious bottleneck for RF energy scavenging. One of the dominant obstacles is the threshold voltage (Vth) of the MOS transistor. In this work we are proposing a simple mechanism to eliminate the Vth dependence in MOS transistor, which inherently improves the DC extraction ability of charge pump. The proposed system is implemented in 180nm CMOS technology and simulated using Cadence Spectre. The extracted DC voltage from RF energy is selected as Figure of Merit. It is found using simulation that the modified charge pump shows a high efficiency in DC extraction from RF signal than the conventional cross coupled rectifier based charge pump.