Shanq-Jang Ruan
National Taiwan University of Science and Technology
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Publication
Featured researches published by Shanq-Jang Ruan.
IEEE Transactions on Consumer Electronics | 2005
Chi-Chia Sun; Shanq-Jang Ruan; Mon-Chau Shie; Tun-Wen Pai
A novel contrast enhancement algorithm is proposed. The proposed approach enhances the contrast without losing the original histogram characteristics, which is based on the histogram specification technique. It is expected to eliminate the annoying side effects effectively by using the differential information from the input histogram. The experimental results show that the proposed dynamic histogram specification (DHS) algorithm not only keeps the original histogram shape features but also enhances the contrast effectively. Moreover, the DHS algorithm can be applied by simple hardware and processed in real-time system due to its simplicity.
IEEE Transactions on Broadcasting | 2011
Fan-Chieh Cheng; Shih-Chia Huang; Shanq-Jang Ruan
Background subtraction involves generating the background model from the video sequence to detect the foreground and object for many computer vision applications, including traffic security, human-machine interaction, object recognition, and so on. In general, many background subtraction approaches cannot update the current status of the background image in scenes with sudden illumination change. This is especially true in regard to motion detection when light is suddenly switched on or off. This paper proposes an illumination-sensitive background modeling approach to analyze the illumination change and detect moving objects. For the sudden illumination change, an illumination evaluation is used to determine two background candidates, including a light background image and a dark background image. Based on the background model and illumination evaluation, the binary mask of moving objects can be generated by the proposed thresholding function. Experimental results demonstrate the effectiveness of the proposed approach in providing a promising detection outcome and low computational cost.
international conference on multimedia and expo | 2006
Yu-Ting Pai; Shanq-Jang Ruan; Mon-Chau Shie; Yi-Chi Liu
Human face detection plays an important role in many applications such as video surveillance, face recognition, and face image database management. This paper describes a fast face detection algorithm with accurate results. We use lighting compensation to improve the performance of color-based scheme, and reduce the computation complexity of feature-based scheme. Our method is effective on facial variations such as dark/bright vision, close eyes, open mouth, a half-profile face, and pseudo faces. It is worth stressing that our algorithm can also discriminate cartoon and human face correctly. The experimental results show that our approach can detect a frame in 111 msecs with the 92.3% detection rate
Iet Circuits Devices & Systems | 2007
Chi-Chia Sun; Shanq-Jang Ruan; B. Heyne; J. Goetze
A computationally efficient and high-quality preserving discrete cosine transform (DCT) architecture is presented. It is obtained by optimising the Loeffler DCT based on the coordinate rotation digital computer (Cordic) algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e. similar to the complexity of the binDCT) without losing quality. After synthesising with TSMC 0.13-mum technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. The experimental results show that the proposed 8-point one-dimensional DCT architecture only consumes 19% of the area and about 16% of the power of the original Loeffler DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT. In this regard, the proposed Cordic-based Loeffler DCT is very suitable for low-power and high-quality encoder/decoders (codecs) used in battery-based systems.
Pattern Recognition | 2010
Yu-Ting Pai; Yi-Fan Chang; Shanq-Jang Ruan
Document image binarization involves converting gray level images into binary images, which is a feature that has significantly impacted many portable devices in recent years, including PDAs and mobile camera phones. Given the limited memory space and the computational power of portable devices, reducing the computational complexity of an embedded system is of priority concern. This work presents an efficient document image binarization algorithm with low computational complexity and high performance. Integrating the advantages of global and local methods allows the proposed algorithm to divide the document image into several regions. A threshold surface is then constructed based on the diversity and the intensity of each region to derive the binary image. Experimental results demonstrate the effectiveness of the proposed method in providing a promising binarization outcome and low computational cost.
Engineering Applications of Artificial Intelligence | 2013
Mu-Hsien Hsieh; Fan-Chieh Cheng; Mon-Chau Shie; Shanq-Jang Ruan
This paper proposes a new median filter using prior information to capture natural pixels for restoration. In addition to being very efficient in logic execution, the proposed filter restores corrupted images with 1-99% levels of salt-and-pepper impulse noise to satisfactory ones. Without any iteration for noise detection, it intuitively and simply recognizes impulse noises, while keeping the others intact as nonnoises. Depending on different noise ratios at an image, two different sets of masked pixels are employed separately for the adoption of candidates for median finding. Furthermore, no limit to the size of mask windows assures that a proper median can be found. The simple logic of the proposed algorithm achieves significant milestones on the fidelity of a restored image. Moreover, the very fast execution speed of the proposed filter is very suitable for being applied to real-time processing. Relevant experimental results on subjective visualization and objective digital measure are reported to validate the robustness of the proposed filter.
systems man and cybernetics | 2011
Fan-Chieh Cheng; Shih-Chia Huang; Shanq-Jang Ruan
In this paper, we propose a novel background subtraction approach in order to accurately detect moving objects. Our method involves three important proposed modules: a block alarm module, a background modeling module, and an object extraction module. The block alarm module efficiently checks each block for the presence of either a moving object or background information. This is accomplished by using temporal differencing pixels of the Laplacian distribution model and allows the subsequent background modeling module to process only those blocks that were found to contain background pixels. Next, the background modeling module is employed in order to generate a high-quality adaptive background model using a unique two-stage training procedure and a novel mechanism for recognizing changes in illumination. As the final step of our process, the proposed object extraction module will compute the binary object detection mask through the applied suitable threshold value. This is accomplished by using our proposed threshold training procedure. The performance evaluation of our proposed method was analyzed by quantitative and qualitative evaluation. The overall results show that our proposed method attains a substantially higher degree of efficacy, outperforming other state-of-the-art methods by Similarity and F1 accuracy rates of up to 35.50% and 26.09%, respectively.
IEEE Transactions on Very Large Scale Integration Systems | 2008
Shanq-Jang Ruan; Chi-Yu Wu; Jui-Yuan Hsieh
Content-addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumption. In this paper, we propose a Block-xor approach to improve the efficiency of low power precomputation-based CAM (PB-CAM). Through mathematical analysis, we found that our approach can effectively reduce the number of comparison operations by 50% on average as compared with the ones-count approach for 32-bit-long inputs. In our experiment, we used Synopsys Nanosim to estimate the power consumption in TSMC 0.35-mum CMOS technology. Compared with the ones-count PB-CAM system, the experimental results show that our proposed approach can achieve on average 30% in power reduction and 32% in power performance reduction. The major contribution of this paper is that it presents theoretical and practical proofs to verify that our proposed Block-xor PB-CAM system can achieve greater power reduction without the need for a special CAM cell design. This implies that our approach is more flexible and adaptive for general designs.
IEEE Transactions on Very Large Scale Integration Systems | 2003
Yen-Jen Chang; Shanq-Jang Ruan; Feipei Lai
Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power, it is one of the most attractive targets for power reduction. This paper presents a two-level filter scheme, which consists of the L1 and L2 filters, to reduce the power consumption of the on-chip cache. The main idea of the proposed scheme is motivated by the substantial unnecessary activities in conventional cache architecture. We use a single block buffer as the L1 filter to eliminate the unnecessary cache accesses. In the L2 filter, we then propose a new sentry-tag architecture to further filter out the unnecessary way activities in case of the L1 filter miss. We use SimpleScalar to simulate the SPEC2000 benchmarks and perform the HSPICE simulations to evaluate the proposed architecture. Experimental results show that the two-level filter scheme can effectively reduce the cache power consumption by eliminating most unnecessary cache activities, while the compromise of system performance is negligible. Compared to a conventional instruction cache (32 kB, two-way) implemented with only the L1 filter, the use of a two-level filter can result in roughly 30% reduction in total cache power consumption. Similarly, compared to a conventional data cache (32 kB, four-way) implemented with only the L1 filter, the total cache power reduction is approximately 46%.
systems, man and cybernetics | 2008
Yi-Fan Chang; Yu-Ting Pai; Shanq-Jang Ruan
Document image binarization plays an important role in many applications such as optical character recognition, automatic bank check processing, and vehicle license recognition. This paper proposes an efficient binarization algorithm with intelligent block size detection. Based on the image characteristic, the document image is automatically divided into several blocks with various sizes. Then, a threshold surface is constructed to derive the binary image. Experimental results show that the proposed method not only provide promising binarization result, but also low computational cost.