Sharad Malik

Certified timing verification and the transition delay of a logic circuit

The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification.<<ETX>>

Propositional SAT Solving

The Boolean Satisfiability Problem (SAT) is well known in computational complexity, representing the first decision problem to be proved NP-complete. SAT is also often the subject of work in proof complexity. Besides its theoretical interest, SAT finds a wide range of practical applications. Moreover, SAT solvers have been the subject of remarkable efficiency improvements since the mid-1990s, motivating their widespread use in many practical applications including Bounded and Unbounded Model Checking. The success of SAT solvers has also motivated the development of algorithms for natural extensions of SAT, including Quantified Boolean Formulas (QBF), Pseudo-Boolean constraints (PB), Maximum Satisfiability (MaxSAT) and Satisfiability Modulo Theories (SMT) which also see application in the model-checking context. This chapter first covers the organization of modern conflict-driven clause learning (CDCL) SAT solvers, which are used in the vast majority of practical applications of SAT. It then reviews the techniques shown to be effective in modern SAT solvers.

Post-Silicon Fault Localization with Satisfiability Solvers

This chapter covers techniques to localize faults in integrated circuits by means of automated satisfiability solvers. These techniques aim at identifying fault candidates for an erroneous execution trace by symbolically checking the consistency between the golden gate level model and the faulty behavior of the prototype chip. Contemporary satisfiability checkers, as well as the use of sliding windows, guarantee the scalability of our approach, which provides both spatial and temporal localization for general faults and is not restricted to a specific fault model.

Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances

Publisher Summary The Boolean satisfiability problem is well-known in computer science. Given a Boolean formula, the goal is to find an assignment to the variables so that the formula evaluates to true or 1, or to prove that such an assignment does not exist. It has many applications, including theorem proving, automatic test pattern generation, and formal verification. Boolean satisfiability (SAT) is a classic NP-complete problem with a broad range of applications. There are many projects that use reconfigurable computing to solve it. This chapter presents a review of the subject with emphasis on a particular approach that employs a backtrack search algorithm and generates solver hardware according to the problem instance. This approach uses the reconfigurability and fine-grained parallelism provided by field-programmable gate arrays (FPGAs). This chapter introduces the SAT formulation and applications. It describes the algorithms to solve the SAT problem and describes in detail two SAT solvers that use reconfigurable computing. Many projects have designed Boolean satisfiability solvers with reconfigurable computing. These projects demonstrate the performance potential of these solvers through fine-grained custom hardware and massively parallel processing. Significant progress has been made in software algorithms as well, and recently, reconfigurable computing solutions have not kept up in incorporating these innovations. This is partly because the tools for reconfigurable computing are not yet mature.