Sharifah Wan Muhamad Hatta

Energy Distribution of Positive Charges in Gate Dielectric: Probing Technique and Impacts of Different Defects

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated.

Negative bias temperature instability lifetime prediction: Problems and solutions

Lifetime of pMOSFETs is limited by NBTI. Conventional slow measurement overestimates lifetime due to recovery. The fast techniques suppress recovery, but cannot give reliable prediction. This work proposes a new lifetime prediction technique that overcomes the shortcomings of both slow and fast methods, based on the As-grown-Generation (AG) model. Its advantages over those based on Reaction-Diffusion (RD) and two-stage models include its simple algorithm, only two fitting parameters at a given temperature, and no need for a kinetic model for the as-grown hole traps. This makes it readily implementable in industrial laboratories for process screening.

Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs

The multigated architecture of FinFETs appear attractive for continued CMOS scaling with the addition of discrete fin sizing that brings a new variable into the design. In this paper, a comprehensive 3-D simulation on 14/16-nm advanced-process FinFET under geometric and process considerations was presented in order to achieve the best possible performance with minimal penalty. Geometric designs, specifically the width and height of the fins as well as the channel lengths, were imposed onto the FinFET, and the impact on the performance merits and devices characteristics was analyzed. The influence of stress engineering, metal gate work function (WF), and doping concentration was further explored for an allowable leakage limit. The simulation suggests that the process-induced stress can boost the 14/16-nm FinFET drain current up to two or three times. It was also found that the channel length is the most critical geometric parameter to affect the performance of both the pFinFET and nFinFET, of which 60% and 50% increases in its respective drain current were observed as the channel length is scaled from 35 nm to 15 nm. In addition, a change in metal WF is found to be the most effective method for the adjustment of threshold voltage.

Predictive As-grown-Generation (A-G) model for BTI-induced device/circuit level variations in nanoscale technology nodes

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer-level test scheme for parameter extraction is developed, reducing test time to 1 hour/device and significantly improving the efficiency for variability tests of nanoscale devices. The model is implemented into a commercial simulator and its applicability for circuit level simulation is demonstrated.

Energy distribution of positive charges in high-k dielectric

Abstract A probing technique to obtain the energy distribution of positive charges in high-k gate stack dielectrics, both within and beyond the substrate bandgap, has been proposed. The energy distribution of different high-k devices has been investigated and attention has been paid to their differences from the single-layered SiON devices. The results obtained from the technique demonstrate the existence of different types of positive charges with each type of them dominating a different energy region. It is observed that the positive charges in high-k stacks are dominated by the as-grown hole traps below the valence band and the cyclic positive charges within the bandgap. The increase in the cyclic positive charges in thinner high-k devices suggests higher NBTI for future CMOS technologies. It is also observed from the energy profile that the metal gate can impact the NBTI substantially. The energy profile obtained from this technique clearly indicates that process optimization is essential for minimizing NBTI in the high-k gate stacks.

Laser Anneal-Induced Effects on the NBTI Degradation of Advanced-Process 45nm High-K PMOS

This paper presents the effects imposed on the reliability of advanced-process CMOS devices, specifically the NBTI degradation, subsequent to the integration of laser annealing (LA) in the process flow of a 45nm HfO2/TiN gate stack PMOS device. The laser annealing temperatures were varied from 900°C to 1350°C. The effects imposed on the NBTI degradation of the device were comprehensively analyzed in which the shifts of the threshold voltage and drain current degradation were observed. The analysis was extended to the effects of the conventional RTA as opposed to the advanced laser annealing process. It was observed that the incorporation of laser annealing in the process flow of the device enhances the NBTI degradation rate of the device, in contrast to the integration of the conventional RTA. Laser annealing subsequent to spike-anneal is observed to improve the reliability performance of the transistor at high negative biases.

Defects evolution involving interface dispersion approaches in high-k/metal-gate deep-submicron CMOS

Abstract The paper proposes a technique to demonstrate energy evolution of amorphous oxides defects from the interface depth dispersion using fast ramp laser spike annealing to achieve super activation, in order to significantly assess their impacts on devices with high-k metal gate by numerical analysis. Recovery of trapped charges in HK/MG technologies is intensively studied and provides its capability for highlighting different positively charged defects within and beyond the silicon band gap. The defects vary significantly with energy level as well as in evolution of the E ′ centers and the interface states densities. The defects in E ′ centers below Fermi energy level are neutral and unstable, which significantly increase above thermal equilibrium during stressing and driven from valence band to above conduction band energy in fast recovery stage. A correlation of the time dependency for the charged trap concentration, interfacial density and the drain current is observed with current degradation due to the trap accumulation. The analysis shows a strong sensitivity to positive bias activation of the dopant thus been considered for the evaluation of the device performance.

Performance of the forward-biased RF-LNA with deep n-well NMOS transistor

This paper presents the merits and demerits of incorporating deep n-well (DNW) implantation NMOS structures in a forward-biased RF-Low Noise Amplifier (LNA). Two versions of a fully-integrated 2.45 GHz LNA design with forward-biasing are presented, a standard transistor version and a DNW transistor version, to evaluate potential improvements or possible degradation in performance by using a DNW structure. The RF performance characteristics of the standard LNA version are compared to the performance of the DNW LNA version. Simulation results had shown that the performance of the power gain and noise figure has been significantly boosted through the use of the DNW transistor structure as amplifying devices.

Reliable Time Exponents for Long Term Prediction of Negative Bias Temperature Instability by Extrapolation

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years.

Scaling impact on design performance metric of sub-micron CMOS devices incorporated with halo

Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial in countering the limitations impose by SCE. This paper investigates the advantages of implementing the halo process into the design of the submicron-CMOS devices. Critical device performance merits and CV characterizations were explored as the device is scaled. Although the use of halo degraded slightly the performance for typically long channel transistor, the merging of halo implants at short transistor shows improvement with high stability of threshold voltage and low off-current. The Drain-induced barrier lowering (DIBL) specifically for the 45nm pMOS and nMOS alone had reduced to 25% and 41% respectively. With careful optimal choice for heavy doped halo of and reverse body biasing, it simultaneously relieved total leakage current by adjusting the threshold voltage.