Sharon X. Ling

Comparison of flip chip technologies on rigid polyimide with respect to reliability and manufacturing costs

Flip chip interconnect technology has seen extensive growth with the demands for electronics miniaturization. Applying flip chip interconnection can potentially achieve smaller size, better performance, higher reliability and, with the development of new materials and processes, lower cost. In this study, the Space Department of the Johns Hopkins University Applied Physics Laboratory is working jointly with HyComp, and Fraunhofer Institute of Reliability and Microintegration, to investigate the feasibility and reliability of several types of interconnect technologies for flip chips. Attentions will be focused on the interconnections between integrate circuits (ICs) and the substrate as they are indicated as weak linkages for long-term reliability. Emerging interconnect technologies, such as applying anisotropic conductive adhesive (ACA), Au stud bumping, and Stud Bump Bonding (SBB), will be discussed in this paper. All assemblies will be subjected to series of reliability tests, including temperature cycling, thermal shock, vibration, 85/spl deg/C/85% RH temperature humidity, and radiation tests. In-situ resistance measurements will be made to continuously monitor performance of interconnects. The test results can be used to evaluate and assess the reliability of the interconnect technology for future space application. Furthermore, a cost comparison of all investigated technologies will be given in this study. Thus we evaluated not only the technological but also the economical potential of each technology.

The MESSENGER Power Distribution Unit packaging design

A Power Distribution Unit (PDU) is being developed by The Johns Hopkins University Applied Physics Laboratory for the MESSENGER (MErcury Surface, Space ENvironment, GEochemistry, and Ranging) spacecraft that will orbit the planet Mercury for one Earth year to complete the global mapping and the detailed characterization of the planets exosphere, magnetosphere, surface, and interior. The PDU contains the circuitry for the spacecraft pyrotechnic firing control, power distribution switching, load current and voltage monitoring, fuses, external relay switching, reaction wheel relay selects, and power system relays. It also supports the Inertial Measurement Unit (IMU) reconfiguration, Integrated Electronic Module (IEM) select relays, solar array drives, propulsion thruster firing control, and propulsion latch valve control. To enable the mission to reach the distant planet, significant weight reduction for all spacecraft electronics must be achieved. This requirement has led to an advanced electronic packaging design that begins with component selection, printed wiring board design with very small feature sizes, and a compact interconnection scheme. The significant challenge in the packaging design of the PDU is how to implement state-of-the-art technologies to minimize system weight and meet the stringent reliability required by the MESSENGER power system. This paper will describe the detailed electronic packaging design of the PDU, including the use of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices instead of conventional mechanical relays, high-density printed wiring board designs with blind and buried vias, and a modular packaging design to achieve significant weight reduction.

Benefits and lessons learned from the use of the compact PCI standard for spacecraft avionics

MESSENGER (MErcury Surface, Space ENvironment, GEochemistry, and Ranging) is a mission to orbit and explore the planet Mercury. MESSENGER will carry out comprehensive measurements for one Earth-year. The subsystem that controls the MESSENGER spacecraft is called the Integrated Electronics Module (IEM). The IEM will operate the MESSENGER spacecraft, store data, and autonomously detect and mitigate onboard faults. In addition to meeting challenging requirements, the IEM must be available for integration on the spacecraft only 18 months after the start of full engineering development. The adoption of the 6U compact PCI (cPCI) standard has simplified the IEM development effort, reducing the time and cost that would otherwise be required. The 6U cPCI standard dictates board dimensions and the backplane electrical interface. The use of the standard has allowed some of the IEM boards to be specified and procured with a competitive selection process in a minimal amount of time. Prototype IEM systems have been assembled using commercially available backplanes, card racks, and Ethernet cards. Low-cost off-the-shelf cPCI tools such as board extenders and bus analyzers have been used to aid development. These components and tools would have to be developed at a significant cost if a proprietary or non-commercial board format had been adopted. The 6U cPCI specification itself does not address board level mechanical and thermal requirements, but features were added to the boards to meet these requirements while retaining compatibility with the cPCI standard. This paper details the benefits and lessons learned that have resulted from the use of the 6U cPCI standard in the development of spacecraft avionics.

A lightweight Integrated Electronics Module (IEM) packaging design for the MESSENGER spacecraft

MESSENGER (MErcury Surface, Space ENvironment, GEochemistry, and Ranging) is a mission to orbit the planet Mercury. The comprehensive scientific data collected through the one-Earth-year orbital mission phase will allow scientists to study and understand the environment and evolution of the innermost terrestrial planet. The five-year cruise phase and the harsh environment of Mercury orbit pose challenges to the spacecraft subsystem design in terms of balancing an extremely tight mass budget with robust thermal and mechanical designs. The packaging design for a low-cost, lightweight Integrated Electronics Module (IEM) is presented in this paper. The commercial 6U Compact Peripheral Component Interconnect (PCI) Printed Wiring Board (PWB) design has been selected to reduce development cost. Several unique features of the IEM packaging design include using the RAD6000 processor developed by BAE Systems in the Main Processor board, 64-Mb Hyundai TSOPs stacked two-high for 1 GB of SDRAM on the Solid-State Recorder Assembly, and a 32-mm Ceramic Column Grid Array as the PCI Bridge chip. The IEM chassis that accommodates five PWBs is designed with thin-wall aluminum for weight savings, and is fabricated by investment casting for cost savings. Extensive thermal and structural analyses have been performed to ensure that the IEM is capable of surviving and functioning during launch, cruise, and orbit. Environment tests have been conducted on the pre-engineering IEM to validate analytical results.

An advanced 3D electronic packaging design for the CONTOUR remote imaging spectrograph digital processor unit

The data processing unit (DPU) of the CONTOUR remote imaging spectrograph (CRISP) is being developed by the Johns Hopkins University Applied Physics Laboratory for the Comet Nucleus Tour (CONTOUR), a NASA Discovery mission to explore the composition of the comets Encke and Schwassmann-Wachmann 3. The DPU design employs an advanced electronic packaging approach with 3-D interconnect that provides flexibility to accommodate future expansion and modification by simply adding or replacing one of its modules. Miniaturization of space electronics involves considerations beyond the usual requirements for small size and low mass. A system approach must be developed and started with the top down deliberations on the design of an electronic architecture suitable for miniaturizing all physical aspects of the electronics design, and continued with considerations at the board, component and chips levels. One important task that has often been ignored, in an electronic package design, is the selection of the connectors and the interconnect architecture between the individual boards. This paper will describe the DPU packaging design, the selection process of the interconnect architecture, and the reliability evaluation of the press-fit connectors used in this design.

Evaluation and implementation of advanced electronic packaging techniques for reliable, cost-effective miniaturized space electronics

Implementing advanced electronic packaging schemes in space electronics design is a desirable, cost-effective way to leverage existing technologies derived from consumer electronics. Demands for faster, better, lighter, and cheaper products have led to many innovative designs in commercial electronics. However, directly using commercially available packaging techniques in space electronics could be extremely risky without careful reliability study and assessment. With many years of experience in developing high-reliability electronics, the Space Department of the Johns Hopkins University Applied Physics Laboratory (JHU/APL) started the process of evaluating, qualifying, and developing commercial advanced packaging techniques for space application with chip-onboard (COB) technology. With our in-house fabrication and coating process, we can improve existing commercial COB technology to survive and function through the entire space mission. We have focused investigations on advanced interconnect methods such as flip-chip technology and high-density printed wiring board implemented with blind and buried microvias.