Sheetanshu L. Pandey

Interval Temporal Logic

The dynamic semantics of VHDL presented in this book is based on Allen’s Interval Temporal Logic [4]. This chapter presents some of the key concepts of this logic. Interval Logic is useful in capturing the timing information contained in a VHDL description. The logic organizes a universe by time intervals, relations between time intervals, and by binding actions (or assertions) to time intervals. VHDL behavior can be defined in terms of time intervals and a set of actions that are performed in these time intervals.

A model of VHDL for the analysis, transformation, and optimization of digital system designs

Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize.

VHDL semantics and validating transformations

Formal models are used to provide an unambiguous definition of the semantics of very high speed integrated circuit hardware description language (VHDL) and to prove equivalences of VHDL programs. This paper presents a formal model of the dynamic semantics of VHDL that characterizes several important features of VHDL such as delta delays, pulse rejection limits, disconnection delays, postponed processes, sequential statements, and resolution functions. The underlying logic is interval temporal logic, which assists in characterizing the timing information contained in a VHDL program. The semantic definition is not dependent on the VHDL simulation cycle since it only defines the net effect of evaluating a VHDL program. It is argued that this declarative style coupled with the inherent advantages of temporal logic makes it possible to validate transformations (or rewrite rules) on VHDL programs and to formally reason about the timing aspects of VHDL. In particular, we present proofs of soundness of rewrite rules such as process folding and signal collapsing, and use temporal logic to derive an algorithm for determining when a given VHDL program is free of transaction preemption.

A semantic model of VHDL for validating rewriting algebras

This paper presents a formal model of the dynamic semantics of VHDL using interval temporal logic. The model uses a declarative style that provides a semantic definition of VHDL independent of the VHDL simulation cycle. Therefore, the model can be used as a platform for comparing alternative and possibly more efficient algorithms for simulating VHDL. Furthermore, optimization techniques for improving the performance of VHDL simulators can be validated against this model. To support this claim we present a proof asserting the validity of process-folding. In contrast to past efforts that concentrate only on design verification, this model is also oriented towards CAD tool optimization. The model is comprehensive and characterizes most of the important features of elaborated VHDL.

Formal semantics and proof techniques for optimizing VHDL models

1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.

Applications of the Dynamic Model

This section examines the applications of the Dynamic Model in formally reasoning about VHDL programs. In particular, the model is used to validate two transformation rules (Sections 9.2 and 9.3) and to derive conditions under which no transaction preemption occurs (Section 9.4). The results derived herein are aimed at CAD tool optimization.

The Dynamic Model

This chapter presents the dynamic semantics of a VHDL description as a declarative definition of the state space evaluated by the description. The state space consists of the values of declared signals and ports in the description.1 Since the net result of evaluating a VHDL description is reflected in the changes in values of its signals, the ‘waveforms’ of signals represent a semantics of the description. Thus, the ultimate goal in the definition of the semantics is to specify a set of time intervals spanning the entire simulation of the given VHDL description and to define the values of all signals in the description in those time intervals. The model presented herein is called the Dynamic Model and is based on the normal form of the Static Model as defined in Chapter 5.

A Framework for Proving Equivalences using PVS

This chapter presents an embedding of the dynamic semitics of VHDL in PVS. The semantics is embedded by defining a set of equivalence axioms between VHDL descriptions. We present a shallow embedding of the semantics that consists of a set of functions that describe the transformations that a signal undergoes during the simulation process.

A Well-Formed VHDL Model

This chapter presents a methodology for defining formally what it means for a Static Model representation of a VHDL description to be well-formed. The well-formedness rules are written as a series of axioms describing conditions which must hold true for the Static Model to be considered correct. Each well-formedness condition is written as an informal requirement with a reference to the appropriate section in the LRM followed by the formal axiom.

The Static Model

This chapter presents a mathematical representation of the static constructs of VHDL. This representation is referred to as the Static Model. The Static Model ignores the elaboration process and assumes that the given VHDL description has been fully elaborated and has correct syntax. It is not one-to-one with VHDL. In fact, many elements of VHDL do not appear in the model. For example, design entities are not presented in the model. They are not necessary. The model need only maintain the leaf level components (e.g., concurrent statements and their constituent subparts) and the netlist specifying their interconnections (i.e., the port hierarchy). In some instances not all of the leaf components that might be expected are present. For example, one might reasonably expect to see a tuple definition for concurrent signal assignment. However, such a tuple definition does not exist; instead, the concurrent signal assignment statement is represented using two distinct tuples, namely the selected concurrent signal assignment and the conditional concurrent signal assignment. This decomposition is easier to formally manipulate and the respective forms have distinct translations to process statements.