Sheng-Wen Chen

Linear radio frequency power detector

In this paper, a design for high dynamic range applicable of power detector by using successive detection logarithmic amplifier (SDLA) configuration consists of PMOS load limiting amplifier and unbalanced source-coupled pairs. This device was been fabricated by TSMC 0.18-µm 1P6M CMOS process. The experimental results show that the dynamic range of the power detector the frequency 900-MHz is almost kept at 39-dB and for frequency 1800-MHz, the dynamic range is 29-dB. Its log-error is kept at ±1-dB and consumes is 16-mW from a 1.8-V supply.

Closed-loop power control of radio frequency power amplifier module with an on-chip embedded power detector

A quad-band GSM/GPRS power amplifier module is designed with a built-in ability of RF power transmitting control. Within the RF power transmitting control loop, a RF power detecting circuit with another reference circuit are embedded together onto the same InGaP/GaAs HBT power amplifier chip to achieve a good temperature compensation. Such power chips are then assembly with a silicon CMOS comparative chip by the multi-chip module technology and functions as a closed- loop power controlled GSM/GPRS power amplifier module. It had successfully demonstrated as play for all quad-band operations (GSM850, EGSM900, DCS1800, PCS1900).

PHEMT SP6T ICs for Quadband GSM Handset Applications

An integrated circuit of quad-band GSM single pole six thru (SP6T) switch is designed with an InGaAs/GaAs PHEMT technology. It had successfully demonstrated as play for all quad-band operations (GSM850, EGSM900, DCS1800, PCS1900). Both requirements of low insertion loss (less than 1 dB) and high isolation are achieved at the same time. Some of termination methods were used to improve the isolation between Tx and Rx.

Mixer-based injection-locked frequency tripler

An injection-locked frequency tripler with a push-push frequency doubler and a mixer core is demonstrated. The core power consumption of this design takes 5.34 mW. The locking range is from 13.5 GHz to 20.8 GHz. If concerning about the output power flatness, the acceptable frequency range is from 15.9 GHz to 17.1 GHz. The output power is −5 dBm. In addition, the harmonic suppression is −15 dB at least for the second harmonic and more than 30dB for the fundamental one. Another attractive feature is the individual locking range for each varactor tuning voltage covers 3.5 GHz at 0 dBm input power.

Low power consumption and wide locking range triple-injection-locked frequency divider by two

A low power consumption and wide locking range triple-injection-locked frequency divider by two is demonstrated. It consists of triple-injection which combines two features of direct injection and tail injection to enhance locking range. The measured locking range is from 10.18 GHz to 15.49 GHz (41.37%) with an injection power of 0dBm. The measured maximum output power is -3.42dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 2.71mW from a 1.2V power supply.

PMOS-switching-biased voltage-control-oscillator

A PMOS switching-biased VCO is investigated and fabricated by using TSMC 0.35 μm CMOS technology with 2.8 V power supply voltage. A switching bias is employed for the PMOS tail transistor to improve the phase noise. Measured tuning range is ranged from 2.87 GHz to 3.2 GHz. At 1 MHz offset from the carrier, the measured phase noise is -118.2 dBc/Hz. The chip takes 0.32 mm2 area. For a 0.35mm process, under the consideration of output power, this design shows better performance over the figure of merit.