Sheng-Yi Huang

Comprehensive Noise Characterization and Modeling for 65-nm MOSFETs for Millimeter-Wave Applications

Using an external tuner-based method, this paper demonstrates a complete millimeter-wave noise characterization and modeling up to 60 GHz for 65-nm MOSFETs for the first time. Due to channel length modulation, the channel noise continues to increase and remains the most important noise source in the millimeter-wave band. Our experimental results further show that, with the downscaling of channel length, the gate resistance has more serious impact on the high-frequency noise parameters than the substrate resistance even in the millimeter-wave frequency.

Power improvement for 65nm nMOSFET with high-tensile CESL and fast nonlinear behavior modeling

In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.

Novel Pseudo-Drain (PD) RF power cell in 0.13 um CMOS technology

This paper proposes a cost-effective RF power cell manufactured in an advanced 0.13 um CMOS technology. Without adding additional masks, cost, and process, the power performance can be improved just by using the standard N-well and shallow-trench-isolation processes to form a higher resistive region. This ldquoPseudo-Drainrdquo structure increases the breakdown voltage to more than 4.3V and is higher than the value of 2.5V of the standard 0.13 um core-MOS transistor. This transistor exhibits a high fTtimesBVDS product of 352 for CMOS power FETs. Cutoff frequency and maximum oscillation frequency of 83 GHz and 124 GHz were achieved at a drain bias of 1.2V, respectively; while the maximum power gain, output power and power-added efficiency were 25.6 dB, 19 dBm, and 55%, respectively. Good RF linearity and noise figure were also obtained, as demonstrated by an OIP3 and NFmin of 28.32 dBm and 0.4 dB. The presented RF power transistor is cost effective and can be used for power amplifier integration in RF-CMOS SOC.

Investigation of High-Frequency Noise Characteristics in Tensile-Strained nMOSFETs

For the first time, the high-frequency noise behavior of tensile-strained n-channel metal-oxide-semiconductor field effect transistors, including their temperature dependency, is experimentally examined. Our experimental results show that with similar saturation voltages, the strained device is found to have larger channel noise than the control device at the same bias point. For given direct-current power consumption, however, due to enhanced transconductance, the strained device has better small signal behaviors (higher ft and fmax) and noise characteristics (smaller NFmin and Rn) than the control device.

Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs

In this paper, temperature-dependent RF small-signal and noise characteristics of silicon-on-insulator (SOI) dynamic threshold voltage (DT) MOSFETs are experimentally examined. In the low-voltage regime, both the cutoff and maximum oscillation frequencies (ft and fmax) tend to increase with temperature. In addition, the inherent body-related parasitics and the series resistance have much more impact on fmax than ft. Besides, we found that the noise stemmed from the body resistance (Rb) would contribute to the output noise current, and degrade the minimum noise figure (NFmin). Our study may provide insights for RF circuit design using advanced SOI DT MOSFETs.

Radio-Frequency Small-Signal and Noise Modeling for Silicon-on-Insulator Dynamic Threshold Voltage Metal–Oxide–Semiconductor Field-Effect Transistors

This paper presents small-signal and noise modeling for radio-frequency (RF) silicon-on-insulator (SOI) dynamic threshold voltage (DT) metal–oxide–semiconductor field-effect transistors (MOSFETs). The inherent body parasitics, such as source- and drain-side junction capacitances, and access body resistance have been incorporated in this model. In addition, the analytical equations useful for parameter extractions are derived. The modeling results show good agreements with the measured data both in RF small-signal and noise aspects up to 12 GHz. Besides, we have made comparisons of important model parameters for DT and standard MOSFETs. The extracted parameters show reasonable trend with respect to applying voltages and channel lengths, which reveals the accuracy of the extraction results using our proposed method.

Effect of Mixed-Mode Electrical Stress on High-Frequency and RF Power Characteristics of SiGe Hetero-Junction Bipolar Transistors

In this study, we investigate the hot-carrier stress effects on the high-frequency and RF power characteristics of Si/SiGe hetero-junction bipolar transistors (HBTs). By simultaneously applying a high collector current density and a high collector–base voltage on Si/SiGe HBTs, because hot carriers will be induced; they will then degrade device performance. This is interesting because this stress condition is similar to the DC bias condition of a current source RF power amplifier, termed as the mixed-mode stress. We find that not only the high-frequency characteristic is adversely affected by but also the output power performance of Si/SiGe HBTs suffers from this electrical stress. In addition, we found that the degradations of the high-frequency and power characteristics of such HBTs are worse in constant-base-current measurement than in constant-collector-current measurement. We finally examined the degradations in terms of parasitic resistance and the ideality factors of base and collector currents using a large-signal model.