Shenghou Liu

Al 2 O 3 /AlN/GaN MOS-Channel-HEMTs With an AlN Interfacial Layer

We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm2/V·s, a high on/off drain current ratio of ~1010, and low dynamic on-resistance degradation.

Enhancement-Mode Operation of Nanochannel Array (NCA) AlGaN/GaN HEMTs

In this letter, enhancement-mode (E-mode) AlGaN/ GaN high electron mobility transistors (HEMTs) were demon- strated based on lateral scaling of the 2-D electron gas channel using nanochannel array (NCA) structure. The NCA structure consists of multiple parallel channels with nanoscale width defined by electron-beam lithography and dry etching. Because of the improved gate control from the channel sidewalls and partially relaxed piezoelectric polarization, the fabricated 2 μm-gate-length NCA-HEMT with a nanochannel width of 64 nm showed a thresh- old voltage of +0.6 V and a higher extrinsic transconductance of 123 mS/mm, compared to -1.6 V and 106 mS/mm for the conventional HEMT with μm-scale channel width. The scaling of threshold voltages, peak transconductance, and gate leakage as a function of the nanochannel width were investigated. Small-signal RF performance of NCA-HEMTs were characterized for the first time and compared with those of conventional HEMTs.

High-Voltage (600-V) Low-Leakage Low-Current-Collapse AlGaN/GaN HEMTs with AlN/SiN x Passivation

An effective passivation technique that yields low off-state leakage and low current collapse simultaneously in high-voltage (600-V) AlGaN/GaN high-electron-mobility transistors (HEMTs) is reported in this letter. The passivation structure consists of an AlN/SiN_x stack with 4-nm AlN deposited by plasma-enhanced atomic layer deposition and 50-nm SiN_x deposited by PECVD. The AlN/ SiN_x-passivated HEMTs with a gate-drain distance of 15 μm exhibit a high maximum drain current of 900 mA/mm, a low off-state current of 0.7 μA/mm at V_DS = 600 V, and a steep subthreshold slope of 63 mV/dec. Compared with the static on-resistance of 1.3 mΩ·cm², the dynamic on-resistance after high off-state drain bias stress at 650 V only increases to 2.1 mΩ·cm². A high breakdown voltage of 632 V is achieved at a drain leakage current of 1 μA/mm .

Analysis of surface roughness in Ti/Al/Ni/Au Ohmic contact to AlGaN/GaN high electron mobility transistors

A mechanism of the formation of the bulges on the surface of Ti/Al/Ni/Au Ohmic contact in AlGaN/GaN high electron mobility transistors is proposed. According to the analysis of TEM images and corresponding electron dispersive x-ray spectra, the bulges were found to consist of Ni–Al alloy in the body and Au–Al alloy surrounding. We deduce that the bulges were formed due to Ni–Al alloy aggregation in some local areas during the rapid thermal annealing process, which accounts for the rough surface morphology.

Characterization of Leakage and Reliability of SiN x Gate Dielectric by Low-Pressure Chemical Vapor Deposition for GaN-based MIS-HEMTs

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole-Frenkel emission at low electric field and Fowler-Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated.

Interface/border trap characterization of Al2O3/AlN/GaN metal-oxide-semiconductor structures with an AlN interfacial layer

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011–1012 eV−1 cm−2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well.

O3-sourced atomic layer deposition of high quality Al2O3 gate dielectric for normally-off GaN metal-insulator-semiconductor high-electron-mobility transistors

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al–O–H and Al–Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 × 1012 cm−2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm2.

Preparation and magnetic properties of MnBi

MnBi with low temperature phase was fabricated by melt-spinning and subsequently annealing. The influence of quenching speeds, compositions and annealing conditions on the formation of low temperature phase MnBi was systematically investigated. It was found the amorphous MnBi ribbons could transform into low temperature phase by heat treatment in a temperature range of 533–593 K. The coercivity of MnBi was greatly improved by porphyrization, and exhibited a positive temperature coefficient. The maximum energy product BHmax of the anisotropic bonded magnet is 7.1 MGOe (56 kJ/m3) and 4.0 MGOe (32 kJ/m3) at room temperature and 400 K.

Correction to “Thermally Stable Enhancement-Mode GaN Metal-Isolator-Semiconductor High-Electron-Mobility Transistor With Partially Recessed Fluorine-Implanted Barrier”

Al2O3/AlGaN/GaN enhancement-mode metalisolator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a partially recessed (Al) GaN barrier was realized by a fluorine plasma implantation/etch technique. By properly adjusting the RF power driving the fluorine plasma, the fluorine plasma is able to produce two desirable results: 1) a well-controlled slow dry etching for gate recess and 2) implanting fluorine ions into the AlGaN barrier. The fluorine ions become negatively charged in the barrier layer and induce a positive shift in the threshold voltage. The proposed MIS-HEMT exhibits a threshold voltage (VTH) of +0.6 V at a drain current of 10 μA/mm, a maximum drive current of 730 mA/mm, an ON-resistance of 7.07 Ω · mm, and an OFF-state breakdown voltage of 703 V at an OFF-state drain leakage current of 1 μA/mm. From room temperature to 200 °C, the device exhibits a small negative shift of VTH (~0.5 V) that is attributed to the high-quality dielectric/F-implanted-(Al) GaN interface and the partially recessed barrier.

AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.