Sheran Alles

In-Vehicle Network Architecture for the Next-Generation Vehicles

The demand for drive-by-wire, telematics, entertainment, multimedia, pre-crash warning, remote diagnostic and software update, etc. will significantly increase the complexity of the future in-vehicle communication networks. New types of communication networks will also be necessary to satisfy the requirements of safety and fuel efficiency, and meet the demand for new features. Different sets of vehicle electronic modules will require different types of networks. For example, drive-by-wire and active collision avoidance systems need fault tolerant networks with time-triggered protocols, to guarantee deterministic latencies; multimedia systems need networks with high bandwidth to transfer video files; and body control electronics need low-bandwidth networks to keep the cost down. As the size and complexity of these networks increase, ease of integration has become a major challenge for design engineers. In todays vehicles, there are mainly two networks: a high-speed network for the power train and a low-speed network for the body electronics. Since the complexity of the network is increasing and the demand for bandwidth is growing, future vehicles will require many partitioned networks. The partitioning of the networks will be done based on the locality as well as the functionality of the modules. One of the challenging issues will be the selection of topology to interconnect various in-vehicle partitions of the network. Interconnection among all in-vehicle partitions of the network is necessary for diagnostics and software updates in various modules. One logical approach for interconnecting various partitions of the network would be via a hierarchical bus. This paper shows various types of hierarchical connections among the partitions of in-vehicle networks. Different partitions may use different protocols. For example, one partition may use the CAN protocol, the second partition may use the TTCAN protocol, the third partition may use the LIN protocol, and so on. The hierarchical bus will be using intelligent switches to facilitate the translation of messages from one protocol to another protocol while the messages will be moving from one partition to another partition. This paper discusses the advantages and disadvantages of various types of hierarchical connections in terms of cost, bandwidth, latency, fault tolerance, and many other features. The paper also presents simulation models that can be used to determine the performance of various types of partitions and network topologies.

Real time hardware-in-the-loop vehicle simulation

The models used to simulate an engine, driveline, vehicle, and tire/road-surface models are described. Several control units was linked together to provide a generic real-time hardware-in-the-loop (HITL) simulation is described. The HITL simulation structure and models were designed generically so that they can be utilized for developing a variety of control systems. Generic real-time HITL simulation can use analytical and experimental data, accepts vehicle test parameters as input, and provides real-time, portable dynamic simulation.<<ETX>>

Transient voltage characterization for automotive 42 volt power systems

The rapid escalation of electrical content in current and future automotive applications has necessitated the need for significant increases in electrical power. To meet this demand, automotive manufacturers are developing 42 volt power distribution systems. 42 volts will better meet the power requirements of these, new features and also permit the electrification of ancillaries up to approximately 10 kW which the present 14 volt power systems cannot practically and economically provide. However, the introduction of higher voltage power systems creates new challenges in regards to circuit protection from voltage transients produced from switched loads. This paper focuses on the transients produced by switching inductive loads on 14 and 42 volt systems. A complete analysis is performed on 14 and 42 volt door lock motors for three different types of switches. Measurements were also made on 14 and 42 volt window motors and air conditioning clutch coils. All measurements are compared to simulated results. This work builds on previous studies of prediction of switch arcing. The results of this study are used to develop new conducted immunity standards for automotive products.

Comparison of ISO 7637 transient waveforms to real world automotive transient phenomena

Modern automotive electronic systems must operate as designed while exposed to transient voltages produced on the vehicles power distribution system via switched inductive loads. ISO 7637-2 presents a number of test pulses that are presumed to simulate the actual transients produced in the vehicle. This paper compares three of those pulses (pulses 1, 3a and 3b) to actual transient events which are the result of contact arcing during deactivation of an inductive load. The paper demonstrates that the pulses 1, 3a, and 3b are overly simplistic representations of a more complex waveform. This over simplification may impact accurate assessment of system robustness in the presence of actual transient events.

The hardware design of a real-time HITL for traction assist simulation

A computer simulation methodology which simulates a vehicle in real-time is presented. The vehicle has been divided into a number of subsystems, and each subsystem is modeled separately. Along with the models, the hardware components of several control units were linked together to provide a generic real-time hardware-in-the-loop (HITL) vehicle simulation especially suited with third-party propriety hardware. Such a model provides the capability to verify analytical and experimental data and adjust the hardware/software of certain vehicle components on the test bench. It also provides powerful, complex, and dynamic real-time simulations yet, because it is portable, it reduces onboard vehicle testing time, which makes it adaptable to include different types of vehicles, and also makes it cost effective. This paper outlines the major features of the simulation models, showing a typical application for traction assist (TA) development. The simulation model was verified for a TA event by taking measurements from an onboard computer while the vehicle was driven on various types of road surfaces. The results obtained experimentally corresponded well with those obtained through simulation. >

An interactive PC-based real-time simulator using an object-oriented approach

An interactive real-time vehicle simulator has been developed on an IBM PS/2 486 PC. The authors describe an object-oriented approach used to logically model the physical system of an automobile. They concentrate on the software issues in a real-time design. This design is specific to a vehicle simulator used for traction control. The software structure reflects the structure of the application problem, since everything can be represented as objects and messages. It promotes a smooth transition from system analysis all the way to the actual code. The inherent parallelism in the software system can be modeled naturally. The data abstraction and encapsulation reduces the interdependencies between the software components and consequently facilitates modification. The inheritance mechanism also allows reuse of the code enhancing maintainability. The application domain and the object model are described in detail.<<ETX>>

A cost-effective bus-based multiprocessor system

The authors present a new bus structure called the generalized bus interconnection. In this bus structure all the processors and memory modules are partitioned into a number of processor and memory groups. A processor group is connected to each memory group by a set of multiple buses. For a fixed number of buses, this new bus structure can support more processors than the conventional bus structures. The generalized bus interconnection proposed achieves results comparable to those for the partial multiple bus systems but is even more cost-effective. Simulation results show that the generalized bus system is the most cost-effective among all the bus-based systems.<<ETX>>

A new arbitration circuit for asynchronous multiple bus multiprocessor systems

In a bus-based multiprocessor system, a bus arbitration circuit is necessary to assign the bus(es) to the requesting devices. The authors first discuss some design flaws of an existing asynchronous arbiter for multiple bus systems, and then present another design for an asynchronous arbiter which is simple, inexpensive and easy to implement. This circuit has been built and tested. The performance of this new arbiter was also measured by developing a software simulation model. The performance was measured in terms of fairness and mean-arbitration-time. The performance results are given.<<ETX>>

A cache coherency scheme for an asynchronous packet-switched shared memory multiprocessor

This paper analyses the problems encountered in designing a bus-based cache coherence protocol for an asynchronous packet switched multiprocessor system having private caches for each processor and describes such an implementation, showing the algorithm used in maintaining cache coherency. Multiple copies of the data are allowed to exist. Since there is no directory that keeps track of all the processors caching data, multiple messages need to be broadcast to all caches whenever coherency needs to be maintained. On the other hand, the scaleable coherent interface (SCI) protocol maintains a doubly linked-list of all caches sharing each data with the head pointer maintained at a memory controller. This paper will compare the above two schemes and discuss their corresponding performance and design issues for both small and large scaleable multiprocessors.<<ETX>>

A single chip high-speed M-to-B arbiter for multiple bus multiprocessor systems

An M-user B-server synchronous arbitration circuit is built on a single chip using NMOS technology. The VLSI layout is modular which consists of 3 basic blocks: Type-1, Type-2, and Type-3. For VLSI layout of each block, one has to perform a few interconnections in order to build M-user B-server arbiter on a single chip. We have justified this statement by building arbiters for 16-user 4-server, 4-user 2-server, and 8-user 2-server. This arbiter design on a single chip can considerably reduce the space for total arbitration circuit in any multiprocessor system. At the same time it is faster and consumes less power.<<ETX>>