Sherif H. K. Embabi

A capacitor cross-coupled common-gate low-noise amplifier

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

Multistage amplifier topologies with nested G/sub m/-C compensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G/sub m/ feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-/spl mu/m CMOS process and is tested using a /spl plusmn/1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58/spl deg/ of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm/sup 2/. Step response shows that the op amp is stable.

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

The design of a 2.4-GHz fully integrated /spl Sigma//spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45/spl deg/-spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm/sup 2/ excluding the 0.5-mm/sup 2/ digital /spl Sigma//spl Delta/ modulator.

Low-voltage class AB buffers with quiescent current control

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 /spl mu/m digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads.

Digital BiCMOS integrated circuit design

Preface. List of Symbols. 1. Introduction. 2. Process Technology. 3. Device Design Considerations. 4. Device Modeling. 5. MOS Digital Integrated Circuits. 6. Bipolar CML Integrated Circuits. 7. BiCMOS Digital Integrated Circuits. 8. BiCMOS Digital Circuit Applications. Subject Index.

Constant-g/sub m/ rail-to-rail CMOS op-amp input stage with overlapped transition regions

Conventional techniques to achieve a constant-g/sub m/ rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. An economical but efficient design technique to overcome these problems is proposed. The proposed technique strategically overlaps the transition regions of the tail currents for the n- and p-pairs to achieve constant overall transconductance. Experimental results demonstrate that g/sub m/ variation can be restricted to within /spl plusmn/4% with improved CMRR and frequency response.

A floating-gate MOSFET D/A converter

The inherent capability of floating-gate MOS transistors, of performing addition of weighted input signals, can be exploited to realize single D/A converter architectures. A single floating-gate MOS device can be used as a D/A converter. Its precision for large number of bits is, however, poor. A parallel D/A architecture using floating-gate MOS transistors is proposed. This architecture is very simple but provides better precision than the single transistor D/A converter. An 8-bit D/A converter is presented and simulated to demonstrate the functionality.

An improved current source for low voltage applications

A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.

Scaling of digital BiCMOS circuits

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling. >

A multistage amplifier topology with nested Gm-C compensation for low-voltage application

To design an operational amplifier for low-voltage applications, cascoding is no longer a suitable technique for achieving high DC gain. Instead, multiple cascaded stages must he used, with each stage a simple (noncascode) inverting or noninverting amplifier. In designing a multistage opamp with multiple feedback loops, special care must be taken to ensure stability. A well-known compensation technique is nested Miller compensation. The complexity of the transfer function of the NMC based multistage amplifiers is reflected on its stability conditions. This makes it difficult to devise a systematic design procedure that yields stable NMC-based amplifiers. A topology using nested transconductance (G/sub m/)-capacitance compensation (NGCC) has a simple transfer function that yields simple stability conditions. These conditions can be exploited to simplify design. The authors show an n-stage NGCC amplifier topology consisting of n nested modules and describe a four-stage implementation using a 2 /spl mu/m CMOS process.