Sherif M. Sharroush

A bitline-driven 1T-1C DRAM readout scheme

In this paper, a novel readout scheme for the one-transistor one capacitor (1T-1C) DRAM will be introduced. The scheme depends on charging the bitline as well as the cell-storage capacitance to a certain level and comparing the charging current with a reference current to disclose the stored data. The factors affecting the sense margin will be discussed. The proposed readout scheme will be verified with simulation using the 45 nm CMOS technology. The proposed scheme achieves 80% and 67% reductions in the average read-cycle time and the average power-delay product, respectively.

1T-1C FRAM cell reading without reference-voltage generation

Reading 2T-2C ferroelectric random-access memory (FRAM) cells does not require generating a reference voltage as this architecture is self-referenced. However, this architecture consumes a relatively large silicon area. So, 1T-1C FRAMs are used instead. Reading 1T-1C FRAMs, however, requires generating a reference voltage that is ideally halfway between the bitline voltage generated in case of “0” reading, V0, and in case of “1” reading, V1. Then, this reference voltage will be compared with the bitline voltage by a sense amplifier. In this paper, a preview of some of the schemes that does not require generating a reference voltage will be introduced. Then, a novel reading scheme that does not require the generation of a reference voltage and depends on using two cascaded inverters is discussed. The proposed scheme will be simulated for the 0.13 μm CMOS technology and shows a 60% reduction in the read access time for stored “1”. The reduction in the read access time can be attributed to the fact that the output data will be taken at a parasitic capacitance that is much smaller than the bitline parasitic capacitance.

A novel variable-gain amplifier based on an FGMOS transistor

In radio-frequency receivers, variable-gain amplifiers (VGAs) are often used in order to compensate for the change of the signal level during the channel transmission and to relax the constraints on the succeeding analog-to-digital converter (ADC). In this paper, a novel VGA is introduced using a floating-gate MOS transistor (FGMOS). The voltage gain, the linearity, the valid region for proper operation, and the sensitivity are discussed and quantitative expressions are derived for them. The performance of this amplifier is verified by simulation adopting the 45 nm CMOS technology with Vdd = 1 V.

Performance optimization of 1T-1C DRAMs

There is no doubt that the one-transistor one-capacitor dynamic random-access memories (1T-1C DRAMs) play the most important role as the main memory in several volatile storage systems. The performance of this type of memories is dependent to a large extent on the size of the cell-storage capacitor, Cs, the bitline-parasitic capacitance, CBL, and the bitline precharge level, Vpre. In this paper, the performance of such memories will be evaluated by a proposed figure of merit (FOM) that takes into account the area, the sense margin, the average power consumption, and the average cycle time in the entire memory chip. A quantitative analysis will be performed in order to derive a compact form for the proposed figure of merit. This figure of merit will be evaluated for a certain technology and for certain ranges of Vpre, Cs, and CBL with the optimum values of these parameters determined. The impact of technology scaling on the performance of the 1T-1C DRAM will also be investigated. The derived expressions for the read-access time and the power consumption will be compared with the simulation results for the 45nm CMOS technology with VDD=1V.

A novel low-latency DRAM based on the bitline-discharge rate

ABSTRACT As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.

A novel high-speed CMOS circuit based on a gang of capacitors

ABSTRACT There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Impact of technology scaling on the performance of DRAMs

There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The metrics that are taken as the criteria for evaluating the performance of the DRAM are the chip area, the power consumption, the cycle time, and the sense margin. The simulation results ascertain this impact.

A novel current-race fast CMOS circuit

There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing density applications. However, its performance degrades with increasing the fan-in. In this paper, a novel fast CMOS circuit that is based on a current race is presented and compared with the conventional CMOS logic from the points of view of area, power consumption, and average-time delay. The scheme is verified by simulation adopting the 45 nm CMOS technology with Vdd = 1 V and a 25% reduction in the average propagation delay for a six-input NAND gate is achieved.

Representing the transistor by an equivalent resistor

During the analysis of circuits containing multi transistors, the researcher is faced with a tremendous problem. This is due to the fact the MOS/BJT transistor is a four/three-terminal device with a large number of specifying parameters. In order to simplify the analysis, the four/three-terminal complicated MOS/BJT transistor can be replaced by a two-terminal fictitious resistor with a proper resistance. In this paper, a procedure is described to find a formula for the equivalent resistance of the MOS or the BJT transistor, and thus simplifying the analysis of such circuits considerably. Also, the procedure is applied to circuits containing a single transistor and to circuits containing series and parallel connections of transistors in order to estimate the propagation delays. The derived formulas are verified by comparison with the simulation results adopting the 65 nm CMOS technology with a power-supply voltage of 1 V.

Performance optimization of MOS current-mode logic

The MOS current-mode logic (MCML) family is suitable for high-frequency applications due to the use of a static current source, thus relatively stabilizing its power consumption. However, there are various tradeoffs in the design of this family due to the contradictions that arise when choosing values for the load resistance or the current-source strength. In this paper, the performance of the MCML family will be investigated by using a figure of merit. The performance metrics will be derived in terms of the design parameters and the values of these parameters that correspond to the optimum performance will be estimated (if found). The analysis will be verified by comparison with the simulation results adopting the 45 nm CMOS technology.