Shigeru Ishii

SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design

We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 /spl mu/m design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm/sup 2/).

Direct Measurement of SET Pulse Widths in 0.2-

Heavy-ion-induced SET-pulse widths in NOR-logic cells fabricated by a 0.2-mum FD-SOI technology are directly measured by using an on-chip self-triggering flip-flop circuit. The pulse widths are distributed from 0.3 to 1.0 ns under a constant LET of 40 MeVmiddot cm 2/mg

\mu

The 128-kb SOI SRAMs without body-ties had a threshold LET of 3.6 MeV/(mg/cm/sup 2/), which was increased to 9.0 MeV/(mg/cm/sup 2/) by adding body-ties. We used a mixed-mode three-dimensional simulation to analyze the effects of the body-ties on SEU resistance for FD SOI SRAMs with 0.2-/spl mu/m design rules. The simulations revealed an increase in the threshold LET from 5.8 to 8.1 MeV/(mg/cm/sup 2/) that was mostly due to the reduced bipolar gain of the parasitic bipolar transistor and partly due to the added capacitance, which were both related to the body-ties.

m SOI Logic Cells Irradiated by Heavy Ions

We designed a phase-locked loop (PLL) operating at 200 MHz using 0.2 µm fully depleted silicon-on-insulator (SOI) technology. By SPICE simulation with an appropriate single-event transient (SET) model, we achieved a radiation-hardened PLL that does not cause a SET upset upon ion irradiation with a linear energy transfer (LET) of 50 MeV-cm2/mg at an areal penalty of 75%.

Analysis of body-tie effects on SEU resistance of advanced FD-SOI SRAMs through mixed-mode 3-D Simulations

Data size of recent balloonborne detector is growing. High speed data readout is one of the key technologies for those detectors. A parallel data bus has been used for sending data with high speed. However, it causes problems in noise, mechanical size and power consumption. We apply the serial data link for our apparatus as a replacement of the parallel data link to solve those problems. We designed the hardware and firmware based on the SpaceWire protocol. Because of simple and flexible routing protocol of SpaceWire, the system was compact and has very high modularity. The protocol is implemented on Alteras FPGAs, APEX20KE and Cyclone. The speed of the serial data link was 48-53 Mbps. The maximum data rate to the computer was 4.5 MB/s.