Shigeto Nakayama

Multilayer stacking technology using wafer-to-wafer stacked method

We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7Ω between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.

A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers

This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.

High density assembly technology using stacking method

We have developed a new 3-dimensional (3D) Wafer-to-Wafer stacking technology in which each wafer was stacked one after another, using a unique Through Silicon Via (TSV) fabricated by wet etching technology and surface-micro bump on the lower wafer. Our Wafer-to-Wafer stacking method use a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This interconnection method is useful that all back-side processes are removed except wafer thinning, and also total stacking process is simplified and shortened. Each wafer is fabricated by using 0.18 um CMOS technology based on 8-inch wafers. Electrical connection between each wafer was almost 100% and interconnection resistance less than 0.7Omega between a TSV of the upper wafer and a micro-bump of lower wafer. Five prototype devices showed sophisticated functionality, and yield in the stacked wafer was over 60%.

Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump

We have developed a unique TSV structure and evaluated the connectivity between TSV and micro-bump. The connection resistances are less than 0.7 ohm and the capacitance of TSV is less than 3 pF, respectively. The electrical connection between each wafer was almost 100% and the functional yield reached more than 60%.