Shigetoshi Nakatake

VLSI module placement based on rectangle-packing by the sequence-pair

The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.

Structured Placement with Topological Regularity Evaluation

This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is a kind of standard representation of a sequence-pair. We extract regular structures from a single-sequence in 0(n), and then evaluate the structures by quantifying the regularity as an objective function. Besides, we propose a new simulated annealing (SA) framework, called dual SA, where we convey a constructive feature to an SA framework, so that it attains a placement balancing the size of regular structures against the area efficiency. In experiments, we apply our structured placement to analog block designs, and reveal the definite advantage that our placements contain many regular structures such as rows and arrays without increasing the chip area and the wire length, compared to the existing placement.

Regularity-oriented analog placement with diffusion sharing and well island generation

This paper presents a novel regularity evaluation of placement structure and MOS analog specific layout techniques called diffusion sharing and well island generation, which are developed based on Sequence-Pair. The regular structures such as topological row, array and repetitive structure are characterized by the way of forming subsequences of a sequence-pair. A placement objective is formulated balancing the regularity and the area efficiency. Furthermore, diffusion sharing and well island can be also identified looking into forming of a sequence-pair. In experiments, we applied our regularity-oriented placement mixed with the constrait-driven technique to real analog designs, and attained the results comparable to manual designs even when imposing symmetry constraints. Besides, the results also revealed the regularity serves to increase row-structures applicable to the diffusion-sharing for the area and wire-length saving.

Consistent floorplanning with hierarchical superconstraints

Sequence-pair-based floorplanning has revealed the limit of its usefulness in very large scale integration layout design, the key issue being that it is nonhierarchical and indifferent to the preceding step of partitioning. This paper restructures the sequence pair enhanced to a pair of logic expressions to accept the constraint induced by the previous step - the balanced bipartition. Since the bipartition is hierarchical in nature, the transferred constraint is called the hierarchical superconstraint. Since floorplanning based on this data structure automatically works cooperatively with the partitioning, it is called the consistent floorplanning, which has potential to store all the feasible floorplans under the constraint induced by any balanced binary search. As a typical example, we focus on clock-tree synthesis by H-tree. Experiments are given to show better achievements in length and wire density for module-based circuits and clock trees.

Self-reforming routing for stochastic search in VLSI interconnection layout

Given a route which connects terminals on a one-layer routing area (Steiner tree), flip is a procedure that makes a current route change its configuration within its peripheral domain. A flip reforms a route by replacing one of its edges with a minimal detour. A route can flip one nearby obstacle. If the obstacle is another route, a more organized operation, called the dual flip, is applied to a pair of routes. The idea is enhanced to 2-layer hv-routing. The performance of flip and dual flip was tested in simulated annealing which reforms a route or a set of routes with respect to the evaluation function of multiple objectives. Some unique and satisfiable results were observed.

Structured analog circuit design and MOS transistor decomposition for high accuracy applications

This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog design based on the transistor array are applicable. Also our test chip shows that design with transistor array can suppress the variation of Vth stemmed from CMP process. Based on this conclusion, we propose a simple framework with transistor array for structured analog layout generation, which involves the transistor decomposition. Using this framework, we generate several layouts for a typical CMOS OPAMP circuit and compare the automatically generated layouts with the manual layouts. Although the layout sizes of the transistor array based OPAMPs are slightly bigger than that of the manual designs, the automatic layout generation is much faster than manually synthesizing the layout.

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts

Our target is automation of analog circuit layout, which is a bottleneck in mixed-signal design. We formulate the layout explicitly considering manufacturing process, and propose an algorithm that consists of simultaneous expression and optimization of placement and routing. The key is that all the cells and wires are represented by rectangles. The algorithm is combined into a commercial tool, and the performance convinced us that the utilization shortens the design time.

A device-level placement with multi-directional convex clustering

A challenge to an automated layout of analog IC starts with the insight into a high quality placement crafted by experts. It has been observed that such a placement comprises clusters corresponding to groups of matched devices and devices are placed faithfully to the drawn schema while the placement is still compacted. This paper proposes a novel device-level placement based on Sequence-Pair which includes an effective representation of clusters extracted from the schema. A key idea is to capture a topological structure of clusters in order to place clusters at as faithful positions to those in the schema. We represent this structure in terms of ABLR-relations which can be translated into Sequence-Pair. In experiments, we tested our algorithm for industrial instances and compared the results with those by manual. We showed that our results were better than manual results by, on average, 12.8% and 18.1% with respect to area and net-length.

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects

This paper addresses CMOS analog circuit synthesis in the nanometer process based on geometric programming models. In the current era of electronic integrated circuit (IC) manufacturing, the channel length modulation λ as well as the layout-dependent effects (LDE) such as the shallow trench isolation (STI) stress and the well proximity effect (WPE) must be considered in the circuit synthesis because of the more and more shrinking process. The STI is a popular isolation between active regions in advanced CMOS technologies but it causes stress and influences the mobility. The WPE is the characteristics variation for devices located near the edge of the well mask. In this paper, we provide the posynomial models of the analog circuit specification taking the λ into account as well as introducing the curve fitting to the STI stress and the WPE based on the BSIM model. In the design case of a typical CMOS op-amp, with these LDE-aware models, we optimized the circuit by the geometric programming (GP) and showed that the optimal results satisfied the specification by the simulation.

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications

This paper addresses the problem of transistor decomposition in channel length direction aiming at structured analog layout generation, manufacturability and low-power applications. We propose a channel decomposition method to generate structured layout for analog circuits with transistor array, and evaluate the error arising from the decomposition in both large and small signal analysis. The measurement results from a test chip suggests that the error can be ignored and the design with transistor array is applicable. Our test chip also demonstrates the effectiveness of design with transistor array with several typical analog circuits.