Shih-Hung Weng

Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control

We propose an explicit numerical integration method based on matrix exponential operator for transient analysis of large-scale circuits. Solving the differential equation analytically, the limiting factor of maximum time step changes largely from the stability and Taylor truncation error to the error in computing the matrix exponential operator. We utilize Krylov subspace projection to reduce the computation complexity of matrix exponential operator. We also devise a prediction-correction scheme tailored for the matrix exponential approach to dynamically adjust the step size and the order of Krylov subspace approximation. Numerical experiments show the advantages of the proposed method compared with the implicit trapezoidal method.

A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation

Fast full-chip time-domain simulation calls for advanced numerical integration techniques with capability to handle the systems with (tens of) millions of variables resulting from the modified nodal analysis (MNA). General MNA formulation, however, leads to a differential algebraic equation (DAE) system with singular coefficient matrix, for which most of explicit methods, which usually offer better scalability than implicit methods, are not readily available. In this paper, we develop a practical two-stage strategy to remove the singularity in MNA equations of large-scale circuit networks. A topological index reduction is first applied to reduce the DAE index of the MNA equation to one. The index-1 system is then fed into a systematic process to eliminate excess variables in one run, which leads to a nonsingular system. The whole regularization process is devised with emphasis on exact equivalence, low complexity, and sparsity preservation, and is thus well suited to handle extremely large circuits.

Worst-case noise prediction with non-zero current transition times for early power distribution system verification

A novel method of predicting the worst-case noise of a power distribution system is proposed in this paper. This method takes into account the effect of the transition time of load currents, and thus allows a more realistic worst-case noise prediction. A dynamic programming algorithm is introduced on the time-domain impulse response of the power distribution system, and a modified Knuth-Yao Quadrangle Inequality Speedup is developed which reduces the time complexity of the algorithm to O(nmlog n), where n is the number of discretized current values and m is the number of zeros of the system impulse response. With the algorithm, the worst-case noise behavior of the power distribution system is investigated with respect to the transition time. Experimental results show that assuming a zero current transition time leads to an overly pessimistic worst-case noise prediction.

Character design and stamp algorithms for Character Projection Electron-Beam Lithography

In this paper, we propose a series of methods, including character design, stencil compaction and layout matching for Character Projection (CP) Electron-Beam Lithography. We solve the problems with emphasis on inter-cell routing including wires and vias. For wire layout, we design a small set of regular characters after layout normalization. Then we partition the layout into several rows and adopt a greedy algorithm for layout matching in each row. For via layout, we utilize a minimum path covering algorithm to group vias into paths, which are contained in characters with bounded length. We devise an efficient method to compact all characters into a stencil with much less area than the total area of characters. Experimental results show that our algorithms achieve up to 83.42% and 67.29% of the maximum improved-throughput by CP against to Variable Shaped Beam (VSB) technology for wire and via layouts, respectively. Our characters can apply for general purpose layouts to save the high cost of generating different stencils for different layouts.

Circuit simulation via matrix exponential method for stiffness handling and parallel processing

We propose an advanced matrix exponential method (MEXP) to handle the transient simulation of stiff circuits and enable parallel simulation. We analyze the rapid decaying of fast transition elements in Krylov subspace approximation of matrix exponential and leverage such scaling effect to leap larger steps in the later stage of time marching. Moreover, matrix-vector multiplication and restarting scheme in our method provide better scalability and parallelizability than implicit methods. The performance of ordinary MEXP can be improved up to 4.8 times for stiff cases, and the parallel implementation leads to another 11 times speedup. Our approach is demonstrated to be a viable tool for ultra-large circuit simulations (with 1.6M ~ 12M nodes) that are not feasible with existing implicit methods.

A novel sequential circuit optimization with clock gating logic

To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating conditions and the next-state function, we propose an iterative optimization technique to minimize the overall timing.

Power grid simulation using matrix exponential method with rational Krylov subspaces

One well-adopted power grid simulation methodology is to factorize matrix once and perform only backward/forward substitution with a deliberately chosen step size along the simulation. Since the required simulation time is usually long for the power grid design, the costly factorization is amortized. However, such fixed step size cannot exploit larger step size for the low frequency response in the power grid to speedup the simulation. In this work, we utilize the matrix exponential method with the rational Krylov subspace approximation to enable adaptive step size in the power grid simulation. The kernel operation in our method only demands one factorization and backward/forward substitutions. Moreover, the rational Krylov subspace approximation can relax the stiffness constraint of the previous works [12][13]. The cheap computation of adaptivity in our method could exploit the long low-frequency response in a power grid and significantly accelerate the simulation. The experimental results show that our method achieves up to 18X speedup over the trapezoidal method with fixed step size.

Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

A novel equalized global link architecture and driver-receiver codesign flow are proposed for high-speed and low-energy on-chip communication by utilizing a continuous-time linear equalizer (CTLE). The proposed global link is analyzed using a linear system method, and the formula of CTLE eye opening is derived to provide high-level design guidelines and insights. Compared with the separate driver-receiver design flow, over 50% energy reduction is observed. The final optimal solution achieves 20-Gb/s signaling over 10 mm, 2.6- μm pitch on-chip transmission line with 15.5-ps/mm latency and 0.196-pJ/b energy using 45-nm technology. Monte Carlo simulation also shows that 3 σ/μ for power and delay variation in the proposed global link are 13.1% and 4.6%, respectively.

An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits

This paper presents a new transient electro-thermal simulation method for fast 3-D chip-level analysis of power electronics with field solver accuracy. The metallization stack and substrate are meshed and solved with 3-D field solver using nonlinear temperature-dependent electrical and thermal parameters, and the active transistors are modeled with table models to avoid time-consuming technology computer-aided design simulation. Two contributions are made to enhance the physical relevance and the computational performance: 1) the capacitive effects, including interconnect parasitic capacitance and gate capacitance of power devices with nonlinear dependence on bias and temperature, are explicitly accounted for and 2) a specialized nonlinear exponential integrator (EI) method is developed to address the considerably different time scales between electrical and thermal sectors. The EI-based transient solver allows the electrical system to step with much larger time steps than in conventional methods, thus the time step gap between the electrical and the thermal simulation is largely reduced.

Eye prediction of digital driver with power distribution network noise

Algorithms featuring fast and accurate estimation of worst-case eye diagram have been proposed to replace the time-consuming random bit simulation in channel design. However, when the interaction between nonlinear I/O circuits and power distribution network (PDN) noise is included, most of those approaches fail to maintain accuracy. Based on the superposition of multiple bit pattern responses (SMBP) concept, Ren and Oh [1] developed an algorithm to fast predict the eye diagram that theoretically captures any nonlinearity in the circuit. In this paper, a test circuit with PDN was constructed to examine the performance of this algorithm. The experiment results show good agreement with the results simulated by long PRBS in HSPICE.