Shijun Lin

Hierarchical Cluster-Based Irregular Topology Customization for Networks-on-Chip

In this paper, a hierarchical cluster-based irregular topology customization method is proposed for Networks-on-Chip (NoC). This method contains three steps: (1) partitioning IPs into many hierarchical clusters; (2) generating a core network; (3) deleting redundant edge routers. Results show that the irregular topologies generated by our hierarchical cluster-based method consume less power when satisfying the bandwidth and port number constraints. Compared with the previous method, our method can save about 15.41% of power averagely for all benchmark applications. Particularly, for MPEG 4 decoder, our method can save 31.62% of power.

The Inference of Link Loss Rates with Internal Monitors

Network tomography has been widely used recently as an method to infer the network internal link-level characteristics by end-to-end measurement. In this paper, we consider the problem of estimating link loss rates using network tomography. The existing methods make the inference based on the whole tree of network, which is very complex for large scale network. To overcome this limitation, we propose a low complexity inference approach named LCIA. In the LCIA, we deploy monitors at internal nodes to reduce the complexity of inferring the link loss rates. It mainly consists of two steps. The first step is to deploy monitors at specific internal nodes to divide the original tree into several sub-trees with minimum depth. The second step is to infer the link loss rates of sub-trees by a new estimator which is an explicit function of loss measurements. The LCIA has the following features. First, it greatly reduces the inference complexity as the inference on the sub-trees is much simpler. Second, it improves the accuracy of the estimated results since the variance of loss estimator on sub-trees with lower depth is smaller than that on the original tree. The analytical and simulation results demonstrate that the LCIA outperforms the existing methods both on computation complexity and inference accuracy.

Inference of link loss rates by explicit estimation

Network tomography has been widely used recently to obtain the network internal characteristics by end-to-end measurement. In this study, the authors consider the problem of estimating link loss rates using network tomography. The existing work based on maximum likelihood estimator (MLE) uses iterative approximation to make the inference, which requires a long execution time for large scale network. To overcome this limitation, the authors propose a fast path-based approach (FPA) by explicit estimation to infer the loss rate of links. Instead of estimating the link loss rates directly, the authors first estimate the path loss rates that are used to derive the link loss rates. In addition, the path loss rates are inferred by a new estimator which is an explicit function of loss observations. The authors evaluate the accuracy of this approach through the analysis of the loss rate estimator and simulation. The estimator is proved to be consistent and have the same asymptotic variance as that of the MLE. The simulation results show that the estimated loss rates using the FPA correctly converge to the real loss rates.

Design Trade-Offs in Packetizing Mechanism for Network-on-Chip

Network-on-Chip (NoC) design methodology is considered as an important trend for large System-on-Chip design because of the bandwidth and power constraints in traditional synchronous bus architecture. In the design of packet-based NoC, packetizing mechanism has great effect on communication performance, area, and energy consumption of NoC. In this paper, we carry out detailed simulation to evaluate several kinds of packetizing mechanisms of NoC based on topology of Ring and Spidergon. Simulation results show that Condition-Waiting adaptive packetizing mechanism (CW-APM) is the best trade-off packetizing mechanism in NoC design.

Design networks-on-chip with latency/ bandwidth guarantees

A method is proposed to guarantee bandwidth (BW) or latency of network-on-chip. This method contains three kernels: traffic classification; flit-based switching; path pre-assignment and link-BW setting. Compared with the traditional circuit-switch method, the proposed method can guarantee the latency between one flits generation in the source node and its reception in the destination node. This method also supports a wide range of traffic types such as latency critical, low BW traffic and streaming data which only have BW requirement. Moreover, router and network interface which support the proposed method are implemented and a maximum latency formula is developed. Simulation and synthesis results show that this method can guarantee the BW and latency well and is relatively low cost.

Universal GALS Platform and Evaluation Methodology for Networks-on-Chip

Abstract A networks-on-chip (NoC) cost-effective design method was given based on the globally-asynchronous locally-synchronous (GALS) interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface (NI), and intellectual property (IP) via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration (VLSI) design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.

Evaluation and Analysis of Packet-Length Effect on Networks-on-Chip *

The network-on-chip (NoC) design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length (ADBL) configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases.

A fast path-based approach to infer link loss rates by explicit estimation

To estimate the link loss rates using network tomography, this paper proposes a Fast Path-based Approach (FPA) by explicit estimation. Instead of inferring the link loss rates directly, we first infer the path loss rates from which we can easily derive the link loss rates. In addition, the path loss rates are inferred by a new estimator which is an explicit function of loss observations. The presented estimator is analytical and only requires simple arithmetic calculation. It is also proved to be consistent and have the same asymptotic variance as that of the maximum likelihood estimator (MLE). The simulation results show that the FPA can accurately estimate the link loss rates.

A Sort-Based Approach to Infer the Network Topology

Topology information plays an important role in network management. The existing methods for topology inference based on end-to-end measurements need a threshold for general topologies, which is difficult to select to ensure the inference accuracy. In this paper, we propose a sort-based approach, named SBA, to infer the general topologies without using a threshold. First, a sort-based clustering algorithm, named SBC-AL, is proposed to cluster a group of nodes in which every node has at least one sibling. In the SBA, the nodes are classified into disjoint groups by a fan-out decrement mechanism. Then the SBA uses the SBC-AL to cluster the nodes group by group from the bottom up to infer the topology. We prove that the SBA is consistent and suitable for general topologies. The simulation results show that the SBA has a good performance in both accuracy and efficiency.

Dual-Channel Access Mechanism for Cost-Effective NoC Design

In this paper, we propose dual-channel access mechanism to design cost-effective NoC based on 2D-mesh topology. Compared with traditional single-channel access mechanism, our scheme greatly increases the throughput and cuts down the average latency with reasonable implementation cost, especially when the traffic load is high.