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Publication
Featured researches published by Shimonishi Hideyuki.
Reconfigurable technology : FPGAs and reconfigurable processors for computing and communications. Conference | 2001
Shimonishi Hideyuki; Murase Tutomu
In this paper, the proposed architecture is described and the results obtained when evaluating it in a typical application program for traffic handling are reported. It is shown that the architecture enables Weighted Round Robin packet scheduling at 4.1 Gbps line speed, in addition to 10 Gbps IP packet forwarding and 2.4 Gbps IP/ATM multi-layer switching.
Archive | 2006
Shimonishi Hideyuki
Archive | 2013
Sun Lei; Sonoda Kentaro; Suzuki Kazuya; Shimonishi Hideyuki; Ishii Hideji
Archive | 2016
Sonoda Kentaro; Shimonishi Hideyuki; Hatano Yoichi; Sasaki Takayuki
IEICE Technical Report; IEICE Tech. Rep. | 2012
Ashida Yuta; Koide Toshio; Shimonishi Hideyuki
IEICE Technical Report; IEICE Tech. Rep. | 2006
Yamasaki Yasuhiro; Shimonishi Hideyuki; Murase Tutomu
IEICE Technical Report; IEICE Tech. Rep. | 2004
Yamasaki Yasuhiro; Shimonishi Hideyuki; Murase Tutomu
Archive | 2015
Sonoda Kentaro; Shimonishi Hideyuki; Hatano Yoichi; Sasaki Takayuki
Archive | 2014
Sun Lei; Suzuki Kazuya; Shimonishi Hideyuki; Sugyou Kazushi
IEICE Technical Report; IEICE Tech. Rep. | 2012
Koide Toshio; Shimonishi Hideyuki
