Shin Kosaka

A 1 kbit Josephson random access memory using variable threshold cells

The variable-thresholds cell has the advantages of simple structure and small size. In order to achieve nondestructive readout, rewriting has been carried out with peripheral circuits consisting of latching logic gates without any superconducting loop. OR-INVERT address decoders powered by a two-phase supply are used instead of the AND decoders of previous Josephson RAM chips. The 1 kbit (256*4 bit) RAM chip was fabricated using an Nb/Al-oxide/Nb tunnel junction technology with a 3 mu m design rule. Experimental results show no failure in the 1028 logic gates of the peripheral circuits, and only a 2% bit failure in the cell plane of 1024 bits. Total power dissipation of the chip, including peripheral logic circuits, is 1.9 mW. A preliminary measurement yields an access time of about 500 ps. >

A 4-bit Josephson computer ETL-JC1

The first computer operation of a 4-b Josephson computer, ETL-JC1 (Electrotechnical Laboratory-Josephson Computer no.1), designed using a reduced instruction set computer (RISC) architecture is described. In the experiment, the computer functions have been verified by executing a computer program installed in a Josephson read-only memory (ROM) at a low repetition frequency. To construct the computer, four Josephson LSI chips including a register and arithmetic logic unit, a sequence control unit, an instruction 1280-b ROM unit, and a 1-kb RAM unit were connected on a nonmagnetic printed circuit board. The Josephson LSI chips were fabricated using Nb/AlO/sub x//Nb tunnel junctions with 3- mu m design rules. The total power dissipation was 6.2 mW in the total circuit, which consists of 22000 junctions including regulators on every chip. On the basis of measurements of the delay times of the logic gates and the access times of the memory chips, it is expected that the program execution in the critical path can be carried out with a single central processing unit in less than 1 ns, resulting in 1 giga-instructions per second (GIPS).<<ETX>>

A Josephson 4 bit RALU for a prototype computer

A Josephson 4 bit register/arithmetic logic unit (RALU) which is adaptable to a prototype computer is discussed. The RALU circuit is designed to be composed of ALU, accumulator, registers for 10 bit instructions, 8 bit address, 4 bit data and carry flag, multiplexers, and so on. It consists of a four-junction logic (4JL) gate family of OR, AND, INVERT, and AMP gates. A complete set of photomasks of the RALU has been generated with the computer-aided-design system which performs an automatic standard cell layout, wiring, and logic check. The RALU chip has been fabricated using a 3 mu m Nb/AlO/sub x//Nb tunnel junction technology. Sixteen power voltage regulator junctions and 1273 logic gates are integrated on the 4.3*5 mm/sup 2/ chip. Operations have been confirmed for all 24 kinds of instructions in the RALU chip. Total power dissipation is 1.66 mW. A delay time of 300 ps has been evaluated for generating the SKIP signal to control the program address in the sequence control unit, which is essential to achieve one instruction execution for every high-speed clock cycle. >

A fully operational 1 kb variable threshold Josephson RAM

A 1-kb Josephson RAM chip in which all bits are operational has been demonstrated. The chip employs a new Josephson memory cell called the variable threshold memory cell. The cell has a simple structure and a wide operating margin. A directly coupled logic circuit has been introduced to drive a memory cell array instead of a superconducting loop circuit as used in previous Josephson RAM chips The directly coupled logic circuit using 4JL (four Josephson-junction logic) gates is superior because it applies a well-defined driving current to the memory cells. As a result, a fully operational Josephson RAM is realized. Experimental results on this RAM are presented

Integrated DC–SQUID Magnetometer

A magnetometer using a refractory material integrated with a pickup coil and a DC superconducting quantum interference device (DC–SQUID) has been developed for biomagnetic applications. It has an overall size of 8 ×9 mm2 and a field resolution of less than 40 fT/ √Hz which is limited by the electronics at frequencies above 20 Hz.

A 1 µm Cross-Line Junction Process

A new fabrication process for all refractory Josephson tunnel junctions with dimensions less than 2.5 µm-square is proposed, in which junctions are formed by reactively ion etching a full wafer junction sandwich using a cross-line patterning method. As a mask of the junction patterning process, a two-layer resist system has been employed for improving the patterning accuracy. The cross-line patterning method has made it possible to fabricate small area junction with small spreads of the maximum critical currents. All niobium nitride (NbN) Josephson junctions with dimensions from 1.25 µm-square to 0.5 µm-square have been integrated on a chip by this method. The standard deviation of the maximum critical currents for 1024 1 µm-square junctions has been measured to be about 4%.

A Josephson 10-b instruction 128-word ROM unit

A Josephson instruction read-only memory unit (IROU) has been demonstrated. The IROU, which is composed of a 10-b*128-word ROM plane, a 6-64 decoder, two multiplexers, and several buffers, stores a program for the Josephson computer ETL-JC1. The ROM plane was designed using two-junction DC-SQUID-type ROM cells, in which the zero ROM cell has no junction and no superconducting loop and one ROM cell has a damping resistor. The peripheral circuits were designed using a 4JL family of OR, AND, INVERT, and AMP gates. The IROU chip was fabricated using a Nb-AlO/sub x/-Nb Josephson tunnel junction IC technology with a 3- mu m design rule. There were 1280 ROM cells and 789 4JL gates integrated on the 5-mm*3.45-mm chip. All 128 words of the ROM plane could be read with a total power dissipation of 1.63 mW. The minimum total access time was measured to be 390 ps. >

A fully operational 1-kbit variable threshold Josephson RAM

A 1-kb Josephson RAM chip in which all bits are operational has been demonstrated. The chip employs a new Josephson memory cell called the variable threshold memory cell. The cell has a simple structure and a wide operating margin. A directly coupled logic circuit has been introduced to drive a memory cell array instead of a superconducting loop circuit as used in previous Josephson RAM chips The directly coupled logic circuit using 4JL (four Josephson-junction logic) gates is superior because it applies a well-defined driving current to the memory cells. As a result, a fully operational Josephson RAM is realized. Experimental results on this RAM are presented