Shinan Wang

The Design and Analysis of Thermal-Resilient Hard-Real-Time Systems

We address the challenge of designing predictable real-time systems in an unpredictable thermal environment where environmental temperature may dynamically change (e.g., implantable medical devices). Towards this challenge, we propose a control-theoretic design methodology which permits a system designer to specify a set of hard-real-time performance modes under which the system may operate. The system automatically adjusts the real-time performance mode based on the external thermal stress. We show (via analysis, simulations, and a hardware testbed implementation) that our control-design framework is stable and control performance is equivalent to previous real-time thermal approaches, even under dynamic temperature changes. A crucial and novel advantage of our framework over previous real-time control is the ability to guarantee hard deadlines even under transitions between modes. Furthermore, our system design permits the calculation of a new metric called thermal resiliency which characterizes the maximum external thermal stress that any hard-real-time performance mode can withstand. Thus, our design framework and analysis may be classified as a thermal stress analysis for real-time systems.

Where does the power go in a computer system: Experimental analysis and implications

In the last few years the power dissipation problem of computer systems has attracted more and more attention. A lot of work has been done to decrease power dissipation and increase energy efficiency. We are still, however, not observing significant decrease of power dissipation. On the contrary, modern computer systems consume ever increasing amounts of energy. Where does the power go in a computer system is a question that many people are concerned with. Through comprehensive experiments and measurements, we observe several phenomenons that are in opposition to our common sense. Many people believe, for instance, that CPU utilization is a good indicator of the power dissipation of CPU. Our experiment results, however, show that CPU utilization is not an accurate reflection of the CPU power. Moreover, we discover that despite the performance improvements it introduces, cache could be a big problem for power reducing. Based on our observations we derive ten implications that are important for energy efficient system design.

Application configuration selection for energy-efficient execution on multicore systems

Modern computer systems are designed to balance performance and energy consumption. Several run-time factors, such as concurrency levels, thread mapping strategies, and dynamic voltage and frequency scaling (DVFS) should be considered in order to achieve optimal energy efficiency for a workload. Selecting appropriate run-time factors, however, is one of the most challenging tasks because the run-time factors are architecture-specific and workload-specific.While most existing works concentrate on either static analysis of the workload or run-time prediction results, in this paper, we present a hybrid two-step method that utilizes concurrency levels and DVFS settings to achieve the energy efficiency configuration for a workload. The experimental results based on a Xeon E5620 server with NPB and PARSEC benchmark suites show that the model is able to predict the energy efficient configuration accurately. On average, an additional 10 % EDP (Energy Delay Product) saving is obtained by using run-time DVFS for the entire system. An off-line optimal solution is used to compare with the proposed scheme. The experimental results show that the average extra EDP saved by the optimal solution is within 5 % on selective parallel benchmarks. We present a hybrid method to achieve an energy efficiency configuration.Our method utilizes concurrency levels, thread allocation, and DVFS settings.We propose a model to capture the relationship between C , P , and T in detail.We apply an analytical speedup model to predict an optimal/nearoptimal configuration.

A Design and Analysis Framework for Thermal-Resilient Hard Real-Time Systems

We address the challenge of designing predictable real-time systems in an unpredictable thermal environment where environmental temperature may dynamically change (e.g., implantable medical devices). Towards this challenge, we propose a control-theoretic design methodology that permits a system designer to specify a set of hard real-time performance modes under which the system may operate. The system automatically adjusts the real-time performance mode based on the external thermal stress. We show (via analysis, simulations, and a hardware testbed implementation) that our control design framework is stable and control performance is equivalent to previous real-time thermal approaches, even under dynamic temperature changes. A crucial and novel advantage of our framework over previous real-time control is the ability to guarantee hard deadlines even under transitions between modes. Furthermore, our system design permits the calculation of a new metric called thermal resiliency that characterizes the maximum external thermal stress that any hard real-time performance mode can withstand. Thus, our design framework and analysis may be classified as a thermal stress analysis for real-time systems.

Safari: Function-level power analysis using automatic instrumentation

Resolving excessive power dissipation of modern computer systems has become a substantial challenge. However, few research projects have targeted on application power analysis or application-aware power management, which becomes a rising factor in energy efficient system design. In this paper, we describe and implement an application function (subroutine call) level profiler, Safari. It can be used to generate power profiles of each function in an automatic manner. The experiment results using NPB parallel benchmark suite show that Safari is able to collect function level run-time information with overhead (16% on average) comparable to gprof. The power profiling results can be used for code optimization, power-aware scheduling, or even computing resource billing for future research.

eCope: Workload-Aware Elastic Customization for Power Efficiency of High-End Servers

Hardware components, especially CPU and memory, have made a lot of progress in terms of energy efficiency in the last decade. However, it is still far from the ideal energy proportional. Motivated by the recent observations that the energy efficiency of hardware components varies to a great extent depending on the workload characteristics, we propose eCope, workload-aware elastic customization for power efficiency of high-end servers, to reduce power consumption by workload aware and hardware customization for servers in datacenters. Our unique contribution is that eCope platform can take advantage of any configurable hardware that fits our assumption to improve the energy proportionality for various kinds of services without knowing the details of the target service. We illustrate three case studies to show how can we apply our idea to typical real-world back-end services (file system, database services and web-based services).

StressBar: a system for stress information collection

The causes of stress and how it affects our behaviors are generally not well understood. The stress research usually requires a large amount of data to analyze possible stress-related factors. The data collection process traditionally is time-consuming and cost-ineffective. To help medical researchers collect the stress information, we propose a tool named StressBar utilizing the powerful data collection capacity of smart phones. In this paper, we will show our design and implementation considerations of StressBar.

Low power cache architectures with hybrid approach of filtering unnecessary way accesses

Power has been a big issue in processor design for several years. As caches account for more and more CPU die area and power, this paper presents using filtering unnecessary way accesses to reduce dynamic power consumption of unified L2 cache shared by instruction and data. Our methods include using Invalid Filter, which could eliminate accesses to cache ways contained invalid blocks, and I/D Filter, which could eliminate accesses to cache ways contained instruction/data access type mismatch blocks, and Tag-2 Filter, which could eliminate accesses to cache ways contained tag lowest 2 bits mismatch blocks. Since the methods reducing the activities happened in cache architecture, dynamical CPU power could be significantly decreased. In the paper, we also propose combining the above methods together(Invalid+I/D+Tag-2 Filter), which is called Way-Filtering Cache, in an attempt to achieve better power saving results. Our evaluations show that, we could obtain 19.6%-47.8% (which is on average 34.3%)improvement on a 64K-4way cache and 19.6%-55.2%(which is on average 39.2%) improvement on a 128k-8way cache comparing to Invalid+I/D Filter, and 6.1%-27.7%(which is on average 16.6%) improvement on a 64K-4way cache and 6.9%-44.4%(which is on average 25.0%) improvement on a 128k-8way cache comparing to Invalid+Tag-2 Filter, respectively. Also, comparing to Tag-Data caches, which is popular used in less-latency-sensitive caches(e.g. unified L2 or Shared Last-LevelCache), our Way-Filtering cache could get 18.3%-29.2%(which is on average 23.1%) improvement on 64K-4way cache, and 27.2% to 50.1%(which is on average 41.1%) improvement on 128K-8way cache.