Shingo Kojima

Microprogram controlled microprocessor having a plurality of internal buses and including transfer register designation system

A microprogram transfer register designation system for a microprogram controlled microprocessor which has a plurality of internal data buses such that there are previously prepared some number of source register sets each designating one source register for each of the internal buses and some number of destination register sets each designating one destination register for each of the internal buses, wherein one of the source register sets and one of the destination register sets is selected when an interregister transfer is executed. A transfer register designation field of a microcode includes at least one transfer inhibit flag for the internal buses.