Shingo Tomohisa

Practical applications of SiC-MOSFETs and further developments

The next generation power modules using SiC-MOSFETs have been developed for over ten years. From our successful results, we have released SiC power modules which have been used in railway vehicles, industrial machines and home appliances, etc. Low on-resistance 3.3 kV SiC-MOSFETs have been realized by JFET doping and they demonstrated a loss reduction of 55% in a traction inverter compared to a conventional system. In the case of a 1.2 kV MOSFET, a 1 cm2 die verified that it can control a large current of over 600 A. For home appliances, we reduce the trade-off between the threshold voltage and channel mobility by a new gate oxide process. High threshold voltage SiC-MOSFETs having a low on-resistance contribute to the low cost installation of SiC-MOSFETs into air conditioners and achieved a loss reduction of 45% in DC converters. For further reduction of conduction loss, we investigated new structures and technologies. Trench SiC-MOSFETs having a bottom p-well verify lower on-resistance and a larger SCSOA than those of planar MOSFETs. The optimization of the dopant concentration in the drift layer and a reduction of wafer thickness verified the reduction of on-resistance. They are expected to contribute to a lower power loss.

Prevention of Cu degradation using in situ N2 plasma treatment in a dual-damascene process

The surface state of copper after an etching process using CF4 gas has been analyzed. Copper surface stability against corrosion is evaluated through a storage test performed under high-humidity conditions after the etching process. The storage test reveals that the copper surface suffered from both corrosion and oxidation. The copper degradation is caused by a postreaction between moisture and residual fluorine, wherein the resulting oxygen-containing copper film features a rough surface morphology. We examined in situ plasma treatments with several gases to reduce corrosive reactions. Results indicate that in situ N2 plasma treatment removes fluorine residue from the copper surface, and that this treatment effectively stabilizes the copper surface against corrosive conditions.

Evaluation of distribution of exchange coupling in CoFe/Ru/CoFe synthetic antiferromagnetic structure after annealing

We investigated the exchange-coupling fields of CoFe/Ru (tRu)/CoFe synthetic antiferromagnetic (SyAF) structures with a Ru underlayer and capping layer before and after annealing at 300 and 350 °C. Exchange-coupling field Hex decreased after annealing and distribution increases in Hex were observed in the structure of smaller tRu, especially at tRu≤0.7 nm. Remanence magnetizations increased at smaller tRu. These results indicate that distribution is caused by the existence of the antiferromagnetic coupling of locally various coupling fields due to annealing. A larger exchange-coupling field after high temperature annealing can be obtained by suppressing the distribution of the exchange coupling in the SyAF structure.

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.

Effect of lanthanum silicate interface layer on the electrical characteristics of 4H-SiC metal-oxide-semiconductor capacitors

Abstract The effect of La-silicate interface layer (IL) on the electrical characteristics of 4H-SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO2 (ALD-SiO2) gate dielectrics was investigated. In addition to a slight reduction in the interface state density (Dit), the surface potential fluctuation was greatly reduced due to the reduction in the fixed charges (Qfix) with La-silicate IL. Moreover, two orders of magnitude reduction in the oxide trap density in the ALD-SiO2 layer adjacent to the La-silicate IL was confirmed. Physical analysis revealed the reduction in carbon concentration and incorporation of La atoms adjacent to the La-silicate IL.

Improvement of SiO 2 /4H-SiC Interface properties by post-metallization annealing

Abstract Electrical characteristics of SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO2 (ALD-SiO2) gate dielectrics were investigated. Post-metallization annealing (PMA) with W gate electrodes at 950 °C showed a large recovery in the flatband voltage toward the ideal value and the hysteresis was reduced to 36 mV. Interface state density (Dit) of 3 × 1011 cm−2/eV was obtained after the PMA for 5 × 103 s. The concentration of the residual carbon atoms in the SiO2 gate dielectrics has been reduced after annealing, suggesting one of the possible origins of the improvements.

Suppression of Short-Circuit Current with Embedded Source Resistance in SiC-MOSFET

This work reports an SiC-MOSFET which replaces a part of the channel resistance with an additional embedded resistance, called a source resistance (Rs). MOSFETs with Rs have higher resistance during short circuit compared with MOSFETs without Rs and suppress short-circuit currents. An improvement of the trade-off relationship between short-circuit capability and on-resistance was obtained with MOSFETs including embedded Rs.

Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs

External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.

Impact of Stripe Trench-Gate Structure for 4H-SiC Trench MOSFET with Bottom Oxide Protection Layer

An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (dBPWs). For the stripe structure, more significant improvements on the specific on-resistance (Ron,sp), gate-source threshold voltage (Vth) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.