Shinji Sugatani

EBDW technology for EB shuttle at 65nm node and beyond

When manufacturing prototype devices or low volume custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We attempt to apply EBDW mainly to critical interconnect layers to reduce the mask expenditure for the reason of technical output reusability. For 65nm node production, new 300mm EB direct writer had been installed. The process technologies have also been developing to meet sufficient qualities and productivities.

CP based EBDW throughput enhancement for 22nm high volume manufacturing

The CP (character projection) based multi-beam EBDW system MCC (Multi Column cell) seems to be most practical from the view point of the extension of single beam CP based methodology which we have already introduced to device production. But drastic enhancement approach is indispensable to attain higher throughput of more than 100 WPH for 22nm node and beyond. The three key factors are the multi-beam number, the cluster chamber number and the CP shot count reduction rate. In this report, we show the estimation results of beam number, cluster chamber number, CP reduction rate and current density to attain the throughput of 100 WPH with MCC.

Applying photolithography-friendly design to e-beam direct writing in 65-nm node and beyond

It is commonly known that maskless lithography is the most effective technology to reduce costs and shorten the time need for recent photo-mask making techniques. In mass production, however, lithography using photo-masks is used because that method has high productivity. Therefore a solution is to use maskless lithography to make prototypes and use optical lithography for volume production. On the other hand, using an exposure technology that is different from that used for mass production causes different physical phenomena to occur in the lithography process, and different images are formed. These differences have an effect on the characteristics of the semiconductor device being made. An issue arises because the chip characteristics are different for the sample chip and the final chip of the same product. This issue also requires other processes to be changed besides switching to the lithography process. In our previous paper, we reported on new developments in an electron-beam exposure data-generating system for making printed images of a different exposure source correspond to each other in lithographic printing systems, which are electron beam lithography and photolithography. In this paper, we discuss whether the feasibility of this methodology has been demonstrated for use in a production environment. Patterns which are generated with our method are complicated. To apply the method to a production environment we needed a breakthrough, and we overcame some difficult issues.

Study of device mass production capability of the character projection based electron beam direct writing process technology toward 14 nm node and beyond

Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing (EBDW) technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count. For the alignment on the some critical layers which have the normally an even surface, the alignment methodology differ from photolithography is required. The process that etches the SiO2 material in the shallow trench isolation is added and then the alignment marks can be detected using electron beam even at the gate layer, which is normally on an even surface. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the 65 nm node device. The condition in our system is checked using self-diagnosis on a regular basis, and scheduled maintenances have been properly performed. Due to the proper system control, more than 10,000 production wafers have been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted to the 32 nm node production with slight modifications. For the 14 nm node and beyond, however, the drastic increment of the shot count becomes more of a concern. The Multi column cell (MCC) exposure method, the key concept of which is the parallelization of the electron beam columns with a CP, can overcome this concern. It is expected that by using the MCC exposure system, those techniques will be applicable to the rapid establishment for the 14 nm node technology.

Optimization of chemically amplified resist for high-volume manufacturing by electron-beam direct writing toward 14nm node and beyond

We investigated a high-resolution chemically amplified resist for introducing a multi-column cell electron-beam directwriting system into the manufacturing of sub-14 nm technology node LSIs. The target of total blur, which leads to an exposure latitude above 10%, is less than 13.6 nm for 14 nm logic node LSIs. We divided the total blur into three terms, forward-scattering, electron-beam and resist. At a 40 nm-thick resist, the forward-scattering blur was calculated as 1.0 nm in lithography simulation, and beam blur was estimated to be 7.1 nm from the patterning results of hydrogen silsesquioxane. We found that there is a proportional relation between resist blur and acid diffusion length by using a new evaluation method that uses a water-soluble polymer. By applying a chemically amplified resist with a short acid diffusion length, resist blur decreased to 14.5 nm. Even though total blur is still 16.2 nm, we have already succeeded in resolving 20 nm line and space patterns at an exposure dose of 79.6 μC/cm2.

Feasibility study of character projection-based electron-beam direct writing for logic LSI wiring including automatically routed area with 14nm node technology case

Multi column cell (MCC) exposure system is a promising candidate for the next generation lithography tool. The concept of MCC is parallelization of the electron beam columns with character projection (CP) [1]. In this paper, we would like to describe current CP techniques being used for product manufacturing. We also would like to introduce CP based EBDW method to draw automatically routed wiring area with 14 nm node technology of 20nm half-pitch (hp) case. Pattern density influence for process margin and shot noise tolerance consideration are discussed. Feasibility study of the model character set for router generated wiring drawing is presented.

Design for electron beam: A novel approach to electron beam direct writing throughput enhancement for volume production

The ordinal shot count reduction in the character projection based electron beam (EB) maskless lithography is done by the recognition of the repeatability of physical design data. Nevertheless, the reduction efficiency is limited to around four times. The new concept of design for electron beam enables a much higher shot count reduction rate of more than ten times and enables a drastic throughput enhancement. Using this method, the authors created an EB friendly design layout data by tracing back to upstream design flow and this is the most characteristic feature of this methodology.

Practical proof of CP element based design for 14nm node and beyond

To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology “CP element based design”. In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.

Characterization of Fogging and Develop-Loading Effects in Electron-Beam Direct-Writing Technology

We investigated long-range critical dimension (CD) error factors, such as fogging and develop loading, to improve CD uniformity in electron-beam direct-writing (EBDW) technology. It was found that the impact of both effects reached 20 mm and the CD of the monitor pattern decreased by no less than 10%. Fogging and develop loading were separated by comparing the newly designed test patterns that were exposed using both EB and a krypton-fluoride excimer laser. We confirmed that the impact of fogging and develop loading by arranging dummy patterns with a density of 40% was estimated to be +8.9 and -18.9% in the CD, respectively. Based on success in separating each effect, fogging and develop loading were decreased by applying an antistatic agent and multipuddle development, respectively.

Practical study on the electron-beam-only alignment strategy for the electron beam direct writing technology

Techniques to introduce of electron beam direct writing (EBDW) technology into the volume production lines for the 65 nm process technology are shown and discussed. In order to apply these techniques in a harmonious way, partial modifications to the current production line infrastructures are required, because those infrastructures have been optimized for the conventional photolithography technology. One of the large differences is with the alignment. For the gate layer, the appropriate solution is to have an additional process step to remove SiO2 material filled in the shallow trench isolation alignment marks before the patterning. For the dual damascene process at the metal layers, careful consideration of the choice between the indirect alignment or the direct alignment is necessary, when the metal layer is aligned to the previous via layer underneath. We expect that these techniques can be used for the advanced node devices as well, while some new structures would be applied on these devices. In addition to the optimizing the alignment mark structures, the appropriate adjustment of EBDW system parameters by advanced process control (APC) is required, in order to have enough overlay accuracy at the actual production use. Although such process control systems are normally optimized to photolithography, we have confirmed that APC system can be also used for the EBDW technology for appropriate overlay accuracy control. Furthermore, the alignment budget in our systems is created and the alignment accuracy in our future system is estimated based on it. Based on the findings from these discussions, we expect that the EBDW with e-beam-only alignment will be applicable for the production of the 11 nm half-pitch process technology node and the beyond.