Shinya Takyu

Novel wafer dicing and chip thinning technologies realizing high chip strength

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thickness of 50 to 200 mum, such damage has to be avoided. In this study, the relationship between chip residue damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1312 MPa are described

A study on chip thinning process for ultra thin memory devices

Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning technologies are important key technologies to achieve it. The manufacturing steps for semiconductor devices are generally classified into steps for patterning semiconductor elements in a wafer, steps for thinning a wafer, steps for dicing semiconductor elements into chips and sealing the chips in packages. Wafers are thinned by means of mechanical in-feed grinding using a grindstone containing diamond particles, resulting in spiral grinding saw marks on the backside of the wafers. Dicing wafers always causes surface chipping, dicing saw marks on the chip side and backside chipping. Such defects on chip faces become sources of cracks, decreasing chip strength. Therefore, the manufacturing process of thin chips must achieve the requirement of no damage on all chip faces. We already proposed a novel wafer thinning process namely a dicing before grinding (DBG) and DBG + mirror finish process on 56th ECTC, and also proposed a novel flip chip process for ultra thin chip on 57th ECTC. Incidentally, the thickness required for a semiconductor chip to work has not yet been determined. In this paper, the memory chip performance test results are described.

Novel Flip Chip Technologies for Ultra Thin Chip

Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning and flip chip technologies are key in achieving it. The typical flip chip manufacturing steps for thin semiconductor devices are as follows. First, semiconductor elements are formed on a wafer. Surface protective tape is attached to the surface of the wafer and backside grinding is performed to make the wafer thin. Then, dicing tape is attached to the backside of the wafer and the wafer is diced from the surface side, using a diamond blade, and divided into chips. Then, the chips are picked up, using pick up needles and bumps are formed on the surface of the chip. Next, seal resin is attached to a substrate, then the surface of the chip is attached to the substrate with the seal resin and flip chip interconnection and sealing are performed to mount the chip. This manufacturing step has some problems. In this paper, a novel thin package manufacturing process is described.

The development of Cleaving — DBG + CMP process

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thicknesses of 50 to 200 µm, such damage has to be avoided. In this study, novel manufacturing process steps for thin semiconductor devices are followed. 1) Irradiating dicing lines of wafer with a laser instead of blade dicing 2) Laminating the wafer surface protective tape 3) Cleaving the wafer into chips 4) Grinding until the final thickness + 5 um, that is simular DBG 5) Mirror finishing by CMP 6) Tape mounting the wafer onto dicing tape or DAF (Die Attach Film) 7) Removing the wafer surface protective tape. We named these process steps Cleaving — DBG.

Development of Bump Support Film (BSF) for expanding the size of WLCSP

Solder joint crack is increasing with increasing of warpage caused by larger Wafer Level Chip Size Package (WLCSP). In this study, we studied new Bump Support Film (BSF) made of back grind tape and thermosetting epoxy resin, which covers the bottom of bumps by heat lamination. We succeeded to form the BSF without voids at the bottom of the bumps by optimizing the thickness of thermosetting epoxy resin layer. We also succeeded to remove residues of BSF at top of the bumps by dicing process. In addition, the board level test of IC chip with BSF shows no electrical defect after reflow process.

Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thicknesses of 50 to 200 μm, such damage has to be avoided. In this study, the relationship between chip residual damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1903 MPa are described.

Development of Double Side Protection Process with Bump Support Film (BSF) and Backside Coating Tape for WLP

Wafer Level Package (WLP) demand has been increasing in proportion to cost competitive devices demand year by year. In order to manufacture the WLP which has higher reliability efficiently, assembly processes with Bump Support Film (BSF) and Backside coating tape has been developed. The BSF consists of Back Grinding tape (BG tape) for getting a function as a wafer thinning and Bump Support Layer (BSL) which is formed on circuit side around the bump for preventing a bump cracking. In addition, the BG tape has bump absorption layer which is thick enough for applying to various bump pitches, heights and chip geometries. In this paper, two main investigations are reported. One is process evaluation with Test Element Group (TEG) and Substrate. The other is comparison of reliability after Thermal Cycle Test (TCT). As a result, we succeeded in forming BSL with a little of residue at the bump top with bump absorption layer which has higher elastic modulus at the large deformation region than that of BSL, and one minute of plasma etching as cleaning of bump surface. We also succeeded in manufacturing double side protected package which has higher reliability than a package without protection at wafer level.

Development of stealth dicing tape for TSV process

TSV (Through silicon via) process has been attractive for smaller and thinner device development. TSV technology makes it possible that vertical communication by electrode between stacked chips. This communication makes devices smaller and thinner because of eliminating of conventional wire bonding. In addition, faster communication and electronic power saving are also advantages. But, Blade dicing of TSV wafer is too difficult because wafer is thinner. There is a possibility that chip crack and chipping may occur. So we select a Stealth dicing (SD) process. SD process can be expected that control of chip crack and chipping. Because there is not vibration such as blade dicing. This paper describes the performance of stealth dicing tape for manufacturing TSV chip.

Novel DAF (Die Attach Film) separation technologies for ultra-thin chip

The SiP enables an easy integration of different types of chip and can be manufactured with few technical innovations. Wafer thinning technologies are key to achieve the SiP. BSG and dicing processes are mechanical processes using diamond grits. These mechanical processes have a high productivity and a low cost as its merits; however, these processes damage such chip surfaces. We already proposed a novel wafer thinning process namely a dicing before grinding (DBG) and DBG + mirror finish process. After DBG process, Die Attach Film (DAF) is diced using a laser dicer. This process is low productivity and high cost. In this study, a novel DAF separation process; spraying a high-pressure air to the DAF has been developed. This novel process achieves high productivity and low cost. We arrived at best process condition to separate the DAF.

Development of DAF (Die Attach Film) with functional gettering agent for metal impurities

Gettering effect which is to trap metal ions on the dangling-bonds located far from the device area is widely known as an inhibition way of this problem. Extrinsic Gettering (EG) method that is formed during back side grinding in the wafer thinning process is one of the most significant technologies considering of reducing cost. However the chip strength has been decreased with increasing the roughness derived from crystal defect. Under these circumstances, we focused on the DAF (Die Attach Film) which is commonly used as an adhesive sheet to stack thin chips and attempted to add a functional gettering agent in this film. We selected Inorganic Ion-Exchange materials as a gettering agent and prepared some samples which have Oxidized Sb for gettering agent. From the result based on this study, the main factor determining gettering effect is an amount of substance of Ion-Exchange materials in the DAF. Its also estimated the quantity of Cu ion adsorption was about 33~50% in the whole of trapped Cu ions in the DAF. And we obtained 38 % Cu ions were adsorbed in the DAF with 10um thickness, which is about 68 % compared to the value from #2000.