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Dive into the research topics where Shiv Kaushik is active.

Publication


Featured researches published by Shiv Kaushik.


IEEE Micro | 2014

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund; Alberto J. Martinez; Atiq Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael N. Derr; Mikal C. Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; Ronak Singhal; Reynold V. D'Sa; Robert S. Chappell; Shiv Kaushik; Srinivas Chennupaty; Stephan J. Jourdan; Steve H. Gunther; Thomas A. Piazza; Ted Burton

Haswell, Intels fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the cores instruction set.


Archive | 2001

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Dion Rodgers; Deborah T. Marr; David L. Hill; Shiv Kaushik; James B. Crossland; David A. Koufaty


Archive | 2001

Coherency techniques for suspending execution of a thread until a specified memory access occurs

David L. Hill; Deborah T. Marr; Dion Rodgers; Shiv Kaushik; James B. Crossland; David A. Koufaty


Archive | 2001

Suspending execution of a thread in a multi-threaded processor

Deborah T. Marr; Dion Rodgers; David L. Hill; Shiv Kaushik; James B. Crossland; David A. Koufaty


Archive | 2005

Mechanism to emulate user-level multithreading on an os-sequestered sequencer

Gautham N. Chinya; Hong Wang; Xiang Zou; James P. Held; Prashant Sethi; Trung A. Diep; Anil Aggarwal; Baiju V. Patel; Shiv Kaushik; Bryant Bigbee; John Paul Shen; Richard A. Hankins; John L. Reid


Archive | 2005

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Hong Wang; John Paul Shen; Hong Jiang; Richard A. Hankins; Per Hammarlund; Dion Rodgers; Gautham N. Chinya; Baiju V. Patel; Shiv Kaushik; Bryant Bigbee; Gad Sheaffer; Yoav Talgam; Yuval Yosef; James P. Held


Archive | 2001

Instruction sequences for suspending execution of a thread until a specified memory access occurs

Shiv Kaushik; James B. Crossland; Deborah T. Marr; Dion Rodgers; David L. Hill; David A. Koufaty


Archive | 2006

Transparent support for operating system services

Gautham N. Chinya; Hong Wang; Richard A. Hankins; Shiv Kaushik; Bryant Bigbee; John Paul Shen; Prashant Sethi; Baiju V. Patel


Archive | 2006

Communication between instruction set architecture base sequencer by heterogeneous resources

Bryant Bigbee; Gautham N. Chinya; Per Hammarlund; Richard A. Hankins; James Paul Held; Shiv Kaushik; Baiju V. Patel; Dion Rodgers; Gad Sheaffer; John Paul Shen; Yoav Talgam; Hong Wang; Yuval Yosef; Hong Zhang; シェアフェル ガド; チンヤ ゴーサム; カウシク,シヴ; ピー. ヘルド ジェイムズ; シェン、ジョン; ロジャーズ ディオン; ハマーランド、パー; パテル バイジュ; ビッグビー ブライアント; ジャン ホン; ワン、ホン; ヨセフ ユヴァル; タルガム ヨアヴ; ハンキンス リチャード


Archive | 2006

Method and apparatus to attain direct communication between accelerator and instruction sequencer

Hong Wang; Hong Jiang; John Paul Shen; Richard A. Hankins; Per Hammarlund; Bryant Bigbee; Dion Rodgers; Gad Sheaffer; Gautham N. Chinya; Yoav Talgam; Baiju V. Patel; Yuval Yosef; Shiv Kaushik; James P. Held

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