Shiyan Hu

Uncertainty-Aware Household Appliance Scheduling Considering Dynamic Electricity Pricing in Smart Home

High quality demand side management has become indispensable in the smart grid infrastructure for enhanced energy reduction and system control. In this paper, a new demand side management technique, namely, a new energy efficient scheduling algorithm, is proposed to arrange the household appliances for operation such that the monetary expense of a customer is minimized based on the time-varying pricing model. The proposed algorithm takes into account the uncertainties in household appliance operation time and intermittent renewable generation. Moreover, it considers the variable frequency drive and capacity-limited energy storage. Our technique first uses the linear programming to efficiently compute a deterministic scheduling solution without considering uncertainties. To handle the uncertainties in household appliance operation time and energy consumption, a stochastic scheduling technique, which involves an energy consumption adaptation variable , is used to model the stochastic energy consumption patterns for various household appliances. To handle the intermittent behavior of the energy generated from the renewable resources, the offline static operation schedule is adapted to the runtime dynamic scheduling considering variations in renewable energy. The simulation results demonstrate the effectiveness of our approach. Compared to a traditional scheduling scheme which models typical household appliance operations in the traditional home scenario, the proposed deterministic linear programming based scheduling scheme achieves up to 45% monetary expense reduction, and the proposed stochastic design scheme achieves up to 41% monetary expense reduction. Compared to a worst case design where an appliance is assumed to consume the maximum amount of energy, the proposed stochastic design which considers the stochastic energy consumption patterns achieves up to 24% monetary expense reduction without violating the target trip rate of 0.5%. Furthermore, the proposed energy consumption scheduling algorithm can always generate the scheduling solution within 10 seconds, which is fast enough for household appliance applications.

Fast Algorithms for Slew-Constrained Minimum Cost Buffering

As a prevalent constraint, sharp slew rate is often required in circuit design, which causes a huge demand for buffering resources. This problem requires ultrafast buffering techniques to handle large volume of nets while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm using the maximum matching technique is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Fourth, buffer blockage avoidance is handled, which makes the algorithms ready for practical use. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve about 90x speedup and save up to 20% buffer area over the commonly used van Ginneken style buffering. The new algorithms also significantly outperform previous works that indirectly address the slew buffering problem.

Gate sizing for cell library-based designs

With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shift, the problem of discrete gate sizing has received significantly less attention than its continuous counterpart. On the other hand, cell sizes of many realistic libraries are sparse, for example, geometrically spaced, which makes the nearest rounding approach inapplicable as large timing violations may be introduced. Therefore, it is highly desirable to design an effective algorithm to handle this discrete gate-sizing problem. Such an algorithm is proposed in this paper. The algorithm is a continuous-solution-guided dynamic-programming-like approach. A set of novel techniques, such as locality-sensitive-hashing-based solution pruning, is also proposed to accelerate the algorithm. Our experimental results demonstrate that 1) the nearest rounding approach often leads to large timing violations and 2) compared to the well-known Couderts approach, the new algorithm saves up to 21% in area cost while still satisfying the timing constraint.

Fast algorithms for slew constrained minimum cost buffering

As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techniques to handle large volume of nets, while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve > 100times speed up and save up to 40% buffer area over the commonly-used van Ginneken style buffering

Fast interconnect synthesis with layer assignment

As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, have proven to be the critical part of a successful timing closure optimization tool. Layer assignment, which was traditionally treated as same as wire sizing, is more effective and friendly in the design flow than wire sizing in the advanced technologies. Techniques for simultaneous layer assignment and buffer insertion with resource control are increasingly important for the quality of results of interconnect synthesis. This paper outlines the importance of layer assignment over wire sizing, and presents efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources

Power grid analysis with hierarchical support graphs

It is increasingly challenging to analyze present day large-scale power delivery networks (PDNs) due to the drastically growing complexity in power grid design. To achieve greater runtime and memory efficiencies, a variety of preconditioned iterative algorithms has been investigated in the past few decades with promising performance, while incremental power grid analysis also becomes popular to facilitate fast re-simulations of corrected designs. Although existing preconditioned solvers, such as incomplete matrix factor-based preconditioners, usually exhibit high efficiency in memory usage, their convergence behaviors are not always satisfactory. In this work, we present a novel hierarchical support-graph preconditioned iterative algorithm that constructs preconditioners by generating spanning trees in power supply networks for fast power grid analysis. The support-graph preconditioner is efficient for handling complex power grid structures (regular or irregular grids), and can facilitate very fast incremental analysis. Our experimental results on IBM power grid benchmarks show that compared with the best direct or iterative solvers, the proposed support-graph preconditioned iterative solver achieves up to 3.6X speedups for DC analysis, and up to 22X speedups for incremental analysis, while reducing the memory consumption by a factor of four.

Pattern sensitive placement for manufacturability

When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers and the printing is more susceptible to lithographic process variations. Although resolution enhancement techniques can mitigate this manufacturability problem, their capabilities are overstretched by the continuous shrinking of VLSI feature size. On the other hand,the quality and robustness of lithography directly depend on layout patterns. Therefore, it becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, the problem of cell placement considering manufacturability is studied. Instead of designing a new cellplacer, our goal is to tune any existing cell placement solution to be lithography friendly. For this purpose, three algorithms are proposed, which are cell flipping algorithm, single row optimization approach and multiple row optimization approach. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between edge placement error (EPE)reduction and wirelength increase. Using lithography simulations, our experimental results on realistic netlists and cell library demonstrate that over 20% EPE reduction can be obtained by thenew approaches while only less than 1% additional wire is introduced.

Economical and Balanced Energy Usage in the Smart Home Infrastructure: A Tutorial and New Results

The smart home infrastructure features the automatic control of various household appliances in the advanced metering infrastructure, which enables the connection of individual smart home systems to a smart grid. In such an infrastructure, each smart meter receives electricity price from utilities and uses a smart controller to schedule the household appliances accordingly. This helps shift the heavy energy load from peak hours to nonpeak hours. Such an architecture significantly improves the reliability of the power grid through reducing the peak energy usage, while benefiting the customers through reducing electricity bills. This paper presents a tutorial on the development of the smart controller to schedule household appliances, which is also known as smart home scheduling. For each individual user, a dynamic programming-based algorithm that schedules household appliances with discrete power levels is introduced. Based on it, a game theoretic framework is designed for multi-user smart home scheduling to mitigate the accumulated energy usage during the peak hours. The simulation results demonstrate that it can reduce the electricity bill by 30.11% while still improving peak-to-average ratio (PAR) in the power grid. Furthermore, the deployment of smart home scheduling techniques in a big city is discussed. In such a context, the parallel computation is explored to tackle the large computational complexity, a machine assignment approximation algorithm is proposed to accelerate the smart home scheduling, and a new hieratical framework is proposed to reduce the communication overhead. The simulation results on large test cases demonstrate that the city level hierarchical smart home scheduling can achieve the bill reduction of 43.04% and the PAR reduction of 47.50% on average.

Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems

This paper proposes a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems that optimizes system energy consumption under stochastic fault occurrences. The task scheduling problem is formulated as an integer linear program where a novel fault adaptation variable is introduced to model the uncertainties of fault occurrences. The proposed scheme, which considers both the dynamic power and the leakage power, is able to handle the scheduling of independent tasks and tasks with precedence constraints, and is capable of scheduling tasks with varying deadlines. Experimental results have demonstrated that the proposed reliability-driven parallel scheduling scheme achieves energy savings of more than 15% when compared to the approach of designing for the corner case of fault occurrences.

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasingly resistive which makes it more difficult to propagate signals across the chip. However, more advanced technologies (65 nm and 45 nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing, however, routability of the design may be hurt. The challenge is to assign minimal amount of wires to thick metals to meet timing constraints. In this paper, the minimum cost layer assignment problem is proven to be NP-Complete. As a theoretical solution for NP-complete problems, a polynomial time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + isin in O(mlog logm ldr n3/isin2) time for 0 < isin < 1, where n is the number of nodes in the tree and m is the number of routing layers. This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. In addition to its theoretical guarantee, the new algorithm is highly practical. Our experiments on 500 test cases demonstrate that the new algorithm can run 2times faster than the optimal dynamic programming algorithm with only 2% additional wire.