Shohreh Sharif Mansouri

Ring oscillator physical unclonable function with multi level supply voltages

In this paper we introduce a new type of Ring Oscillator PUF (RO-PUF) in which the inverters composing the ring oscillators can be supplied by independent voltages. This new RO-PUF can improve the reliability of the PUF in case of temperature variations.

An algorithm for constructing a fastest Galois NLFSR generating a given sequence

The problem of efficient implementation of security mechanisms for advanced contactless technologies like RFID is gaining increasing attention. Severe constraints on resources such as area, power consumption, and production cost make the application of traditional cryptographic techniques to these technologies a challenging task. Non-Linear Feedback Shift Register (NLFSR)-based stream ciphers are promising candidates for cryptographic primitives for RFIDs because they have the smallest hardware footprint of all existing cryptographic systems. This paper presents a heuristic algorithm for constructing a fastest Galois NLFSR generating a given sequence. The algorithm takes an NLFSR in the Fibonacci configuration and transforms it to an equivalent Galois NLFSR which has the minimal delay. Our key idea is to find a best position for a given feedback connection without changing the positions of the other feedback connections. We use a technology dependent cost function which approximates the delay of an NLFSR after the technology mapping. The experimental results on 57 NLFSRs used in existing stream ciphers show that, on average, the presented algorithm allows us to decrease the delay by 25.5% as well as to reduce the area by 4.1%.

An architectural countermeasure against power analysis attacks for FSR-Based stream ciphers

Feedback Shift Register (FSR) based stream ciphers are known to be vulnerable to power analysis attacks due to their simple hardware structure. In this paper, we propose a countermeasure against non-invasive power analysis attacks based on switching activity masking. Our solution has a 50% smaller power overhead on average compared to the previous standard cell-based countermeasures. Its resistance against different types of attacks is evaluated on the example of Grain-80 stream cipher.

An Improved Hardware Implementation of the Grain Stream Cipher

A common approach to protect confidential information is to use a stream cipher which combines plain text bits with apseudo-random bit sequence. Among the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based ones provide the best trade-off between cryptographic security and hardware efficiency. In this paper, we show how to further improve the hardware efficiency of the Grain stream cipher. By transforming the NLFSR of Grain from its original Fibonacci configuration to the Galois configuration and by introducing new hardware solutions, we double the throughput of the 80 and 128-bit key 1 bit/cycle architectures of Grain with no area and power penalty.

An improved hardware implementation of the grain-128a stream cipher

We study efficient high-throughput hardware implementations of the Grain-128a family of stream ciphers. To increase the throughput compared to the standard design, we apply five different techniques in combination: isolation of the authentication section, Fibonacci-to-Galois transformation of the feedback shift registers, multi-frequency implementation, simplification of the pre-outputs functions and internal pipelining. The combined effect of all these techniques enables an average 56% higher keystream generation throughput among all the ciphers, at the expense of an average 8% area penalty, an average 4% power overhead and a 21% slower keystream initialization phase. An alternative combination of techniques allows an average 23% throughput improvement in all phases.

A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding

Cyclic Redundancy Check codes (CRC) are widely used in data communication and storage devices for detecting burst errors. In applications requiring high-speed data transmission, multiple bits of an CRC are computed in parallel. Traditional methods for constructing an Linear Feedback Shift Register (LFSR) generating k bits of an CRC in parallel are based on computing kth power of the connection matrix of the LFSR. We propose an alternative method which is based on computing kth power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation and we keep the transition relation partitioned. This allows us to bound the size of BDDs by O(n2), where n is the size of the LFSR. Our experimental results show that the presented algorithm asymptotically improves the complexity of previous approaches.

A countermeasure against power analysis attacks for FSR-based stream ciphers

In this paper we analyze the power characteristics of Feedback Shift Registers (FSRs) and their e ect on FSR-based stream ciphers. We introduce a technique to isolate the switching activity of a stream cipher by equalizing the current drawn from the cipher with lower power overhead compared to previously introduced countermeasures. By re-implementing the Grain-80 and the Grain-128 ciphers with the presented approach, we lower their power consumption respectively by 20% and 25% compared to previously proposed countermeasures.

Secure Key Storage Using State Machines

In hardware implementations of cryptographic systems, secret keys are commonly stored in an on-chip memory. This makes them prone to physical attacks, since the location of a memory on a chip in usually easy to spot. We propose to encode secret keys using a state machine which can be concealed in the rest of the logic on a chip. We present an heuristic algorithm which constructs a minimal state machine for a given set of secret keys. We show that, by using m-ary encoding, we are able to construct state machines which are smaller than the ones constructed using binary encoding. The presented algorithm is feasible for storing up to 1 Mbits of random data.

Protecting Ring Oscillator Physical Unclonable Functions Against Modeling Attacks

One of the most common types of Physical Unclonable Functions (PUFs) is the ring oscillator PUF (RO-PUF), a type of PUF in which the output bits are obtained by comparing the oscillation frequencies of different ring oscillators. One application of RO-PUFs is to be used as strong PUFs: a reader sends a challenge to the RO-PUF and the RO-PUF’s response is compared with an expected response to authenticate the PUF. In this work we introduce a method to choose challenge-response pairs so that a high number of challenge-response pairs is provided but the system has a good tolerance to modeling attacks, a type of attacks in which an attacker guesses the response to a new challenge by using his knowledge about the previously-exchanged challenge-response pairs. Our method targets tag-constrained applications, i.e. applications in which there are strong limitations of cost, area and power on the system in which the PUF has to be implemented.

Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers

Feedback Shift Register (FSR) based stream ciphers are one of the most promising new groups of cryptographic algorithms, which target applications characterized by strong power, area and cost constraints. Due to high sensibility against power analysis attacks, there is a strong need for countermeasures which increase the immunity of this class of ciphers without introducing large power and area overheads. In this paper we study analog multi-level countermeasures which can protect FSR-based stream ciphers against Differential Power Analysis (DPA) attacks, with lower power overhead compared to alternative solutions that can be found in literature. We highlight a trade-off between power consumption and security, and propose an approach which ensures at the same time low power overhead and high security against power analysis attacks.