Shoji Shukuri

A semi-static complementary gain cell technology for sub-1 V supply DRAM's

A new semi-static complementary gain cell for future low power DRAMs has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 /spl mu/m/sup 2/ cell size is achieved by using a 0.25 /spl mu/m design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography. >

Future BiCMOS technology for scaled supply voltage

A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.<<ETX>>

A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<<ETX>>

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<<ETX>>

Electrical Properties of Focused-Ion-Beam Boron-Implanted Silicon

Electrical properties of 16 keV, focused-ion-beam (FIB) (beam diameter: 1 µm, current density: 50 mA/cm2) boron-implanted silicon layers have been investigated as a function of beam scan speed and ion dose, and compared with those obtained by conventional implantation (current density: 0.4 µA/cm2). High electrical activation of the FIB implanted layers is obtained by annealing below 800°C as a result of the increase in amorphous zones created in the implanted layers. Amorphous zone overlapping is assumed to occur at FIB implantation doses of 3–4×1015 ions/cm2 from the results of electrical activation and the carrier profile of implanted regions annealed at low temperature, if beam scan speed is lowered to about 10-2 cm/s.

Quasi-complementary BiCMOS for sub-3-V digital circuits

The authors describe a quasi-complementary BiCMOS (QC-BiCMOS) circuit scheme for the low-supply-voltage deep-submicrometer regime. A QC-BiCMOS performs twice as fast as a CMOS even at a 2.5-V supply without a p-n-p bipolar transistor. Key circuits for this low-voltage performance are a separation between the base of the pull-up bipolar and the base of a quasi-p-n-p and the carefully designed base discharging circuit. A quasi-p-n-p combination of a pMOS and an n-p-n bipolar based on these circuits shows an equivalent cutoff frequency of over 10 GHz. The delay expressions for the QC-BiCMOS are analyzed and compared with the conventional BiCMOS. A 0.3- mu m fully loaded three-input NAND gate was fabricated, verifying that the QC-BiCMOS has more than twice the performance leverage over the conventional BiCMOS and the CMOS at a sub-3-V supply. >

Focused ion beam gallium implantation into silicon

The electrical properties and lattice disorders of 50 keV, focused ion beam (FIB) gallium-implanted silicon layers have been investigated as a function of beam scan speed and ion dose. The critical dose for continuous amorphous layer formation is 8 ∼ 10 × 1013 ions/cm2, when the beam scan speed is lowered to about 10−2 cm/s. This is about 1/3 that of conventional ion implantation. The increase in secondary defect formation after annealing is also observed as the beam scan speed decreases under implantation conditions close to the critical dose. However, the effect of high dose rate on the electrical activation of gallium atoms and critical dose reduction is not as significant as with FIB implantation by a lighter ion mass, such as boron. The results are compared with those obtained by conventional ion implantation.

Molecular Scale E-Beam Resist Development Simulation for Pattern Fluctuation Analysis

To better understand nanometer scale pattern fluctuation in lithography, we present a new model for electron-beam exposed (poly)methyl-methacrylate resist development, which considers the molecular scale material structure. The polymer chains in the resist are represented as spheres with a radius proportional to the square root of the chain length. Monte Carlo electron scattering simulation in the resist gives the local absorbed energy, which in turn sets the local molecular weight distribution. The development model uses the Poisson probability for removing each surface polymer chain in a small time step. The Poisson removal rate is derived using a mass equivalence with macroscopic etch rate models. The simulations predict the macroscopic shape of patterned resisi features as well as microscopic surface roughness and nanometer scale line-edge variation. Observations with atomic force microscopy confirm the simulation results, including 10 nm edge variation and rough developed surfaces at exposures doses near the transition from low etch rate to high etch rate.

High Dose Rate Effect of Focused-Ion-Beam Boron Implantation into Silicon

The effect of high-dose-rate, 16 keV focused-ion-beam (FIB) B+ implantation into Si has been investigated as a function of current density and beam-scan speed. It is shown by µ-RHEED (micro-probe reflection high-energy electron diffraction) observation that the increase in electrical activation of implanted B atoms at such low temperature annealing as 600°C closely correlated with the increase in amorphous zones produced. It is also found that continuous amorphous layer formation occurs with a 1–2×1015 ions/cm2 (one order lower than for conventional implantation) when both implantation conditions of high current density and slow scan speed (e.g. 20 mA/cm2 and 6×10-3 cm/s) are satisfied. The reason for amorphous zone formation enhancement by FIB implantation is discussed.

Focused phosphorus ion beam implantation into silicon

Abstract Phosphorus implantation into (100) silicon using a 32-keV focused ion beam is investigated from the standpoints of electrical properties and damage to the implanted layers. Phosphorus ions are extracted from the PtPSb alloy liguid-metal-ion source. Electrical properties are measured by isochronal annealing with Hall measurements and radiation damage is evaluated using a transmission electron microscope. Compared with the conventional implantation method, focused ion beam implantation causes heavier radiation damage and forms amorphous layers at a dose of 2 × 10 14 cm −2 due to high current density.