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Dive into the research topics where 寿倫 佐藤 is active.

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Featured researches published by 寿倫 佐藤.


Proc. of 13th Workshop on Synthesis and System Integration of Mixed Information Technologies | 2006

Multiple Clustered Core Processors

Toshinori Sato; 寿倫 佐藤; Akihiro Chiyonobu; 昭宏 千代延

This paper proposes multiple clustered core processors as a solution that attains both low power consumption and easy programming facility. Considering the current trend of increasing power consumption and temperature, a lot of CPU venders have shipped or announced to ship multiple core processors. Especially, recent studies on heterogeneous multiple core processors show that they are more efficient in energy utilization than homogeneous ones. However, they request programmers to consider complex task scheduling since the size of every task always has to match the performance of core where it is allocated. Multiple clustered core processors relieve them from such a tedious job. Simulation results show that a multiple clustered core processor consumes slightly more power than a heterogeneous multiple core processor. However, in a case, the heterogeneous multiple core processor cannot solve a severe task scheduling problem, while the multiple clustered core processor can.


The 14th Workshop on Synthesis And System Integration of Mixed Information technologies | 2007

Critical Issues Regarding A Variation Resilient Flip-Flop

Toshinori Sato; Yuji Kunitake; 寿倫 佐藤; 勇次 国武


Proceedings of Cool Chips X | 2006

A Multi-Performance Processor for Low Power Embedded Applications

Yuichiro Oyama; Tohru Ishihara; Toshinori Sato; Hiroto Yasuura; 亨 石原; 寿倫 佐藤; 寛人 安浦


VLSI-SoC | 2008

Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops

Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; 勇次 国武; 寿倫 佐藤; 寛人 安浦; ユウジ クニタケ; トシノリ サトウ; ヒロト ヤスウラ


Proceedings of the 4th International Workshop on Dependable Embedded Systems | 2007

Dependability-Performance Trade-off on Multiple Clustered Core Processors

Toshimasa Funaki; 敏正 舟木; Toshinori Sato; 寿倫 佐藤


情報処理学会論文誌 | 2008

Canary: A Variation Resilient FF to Eliminate Design Margin for Energy Reduction

寿倫 佐藤; 勇次 国武; Toshinori Sato; Yuji Kunitake


SLRC Presentations | 2007

Ultra Low Power (ULP) Challenge in System Architecture Level : New architectures for 45-nm, 32-nm era

Toshinori Sato; 寿倫 佐藤; トシノリ サトウ


SLRC Papers Database | 2006

A Preliminary Evaluation of Timing-Speculative Instruction Collapsing

Toshinori Sato; 寿倫 佐藤; Akihiro Chiyonobu; 昭宏 千代延


Distributed Computing | 2006

Utilizing Data Compression to Improve Cache Performance in Multicore Processors with Dedicated Caches

義崇 伊藤; Yoshitaka Ito; 昭宏 千代延; Akihiro Chiyonobu; 寿倫 佐藤; Toshinori Sato


日本信頼性学会誌 : 信頼性 | 2013

4.7 カナリアFF(第4章:素子特性ばらつき, ディペンダブルVLSIシステム)

寿倫 佐藤; 憲 矢野; 寛人 安浦

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昭宏 千代延

Kyushu Institute of Technology

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勇次 国武

Kyushu Institute of Technology

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Akihiro Chiyonobu

Kyushu Institute of Technology

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Shingo Watanabe

Kyushu Institute of Technology

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慎吾 渡辺

Kyushu Institute of Technology

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