Shouchang Chen

A Hybrid SET/MOS Majority Logic Circuit

This chapter proposes a novel majority logic circuit using single-electron transistor (SET) and metal–oxide–semiconductor (MOS) transistor. The majority logic circuit comprises a P-channel metal-oxide-semiconductor (PMOS) transistor, an N-channel metal-oxide-semiconductor (NMOS) transistor, and a SET. The SET/MOS hybrid architecture presents the merits of both the SET and the MOS circuit. The proposed circuit has the advantages of low power dissipation, small feature size, and large output swing. The simulation program with integrated circuit emphasis (SPICE) compact macro model is used to describe the behavior of the SET. The performance of the SET/MOS hybrid majority logic circuit is simulated by the HSPICE simulator. The simulation result shows that the hybrid circuit can operate well as a majority logic gate at the room temperature.