Shouhei Kousai

A 19.7 MHz, Fifth-Order Active- RC Chebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme

A fifth-order LPF with a quality factor (Q) tuning circuit has been implemented for draft IEEE802.11n in a 0.13 CMOS technology. The proposed Q tuning technique realizes a low-power 19.7 MHz, active-RC Chebyshev LPF. The filter has dB gain, 30 nV/Hz1/2 input-referred noise, 113 dBmuV input , P 1dB,draws 7.5 mA current from 1.5 V supply, and occupies an area of 0.2 mm2.

An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement

Non-constant envelope modulation schemes have become commonplace in cellular applications due to their higher spectral efficiency. Linear PAs driven by an RF transmitter are usually used to generate these signals faithfully at the expense of power efficiency. Separate processing of amplitude and phase information (e.g., EER or polar modulation) has been proposed [1] as a way of improving the system power efficiency. However, many of these schemes require an efficient high-power low-frequency supply modulator to reconstruct the amplitude information. This can be done, for instance, using a switching DC-to-DC converter with its own limitations in efficiency, bandwidth, and area that also requires an external inductor [2]. Even for an ideal supply modulator, the amplitude dynamic range of the PA itself is limited by the gate-to-drain feedthrough and its associated AM-to-AM and AM-to-PM conversion. (For example, in [3] a 10dB change in the supply results in a 5° phase shift at the output.) Although a digitally-modulated polar PA [4] has been shown as a possible solution at lower power levels, its implementation in a wideband watt-level fully-integrated CMOS PA for non-constant modulation has not yet been demonstrated.

A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter

A single-chip Bluetooth transceiver in 0.18/spl mu/m CMOS integrates a direct VCO modulation transmitter and 1.5MHz-IF receiver to reduce power consumption and cost. The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm.

Throughput enhancement strategy of maskless electron beam direct writing for logic device

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P and R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

This paper presents a digital polar Doherty power amplifier (PA) fully integrated in a 65 nm bulk CMOS process. It achieves +27.3 dBm peak output power and 32.5% peak PA drain efficiency at 3.82 GHz and 3.60 GHz, respectively. The proposed digital Doherty PA architecture optimizes the cooperation of the main and auxiliary amplifiers and achieves superior back-off efficiency enhancement (a maximum 47.9% improvement versus the corresponding Class-B operation). This digital intensive architecture also allows in-field PA reconfigurability which both provides robust PA operation against antenna mismatches and allows flexible trade-off optimization on PA efficiency and linearity. Transformer-based passives are employed as the Doherty input and output networks. The input 90 ° signal splitter is realized by a 6-port folded differential transformer structure. The active Doherty load modulation and power combining at the PA output are achieved by two transformers in a parallel configuration. These transformer-based passives ensure an ultra-compact PA design (2.1 mm 2) and broad bandwidth (24.9% for -1 dB P out bandwidth). Measurement with 1 MSym/s QPSK signal shows 3.5% rms EVM with +23.5 dBm average output power and 26.8% PA drain efficiency. Measurement with 16-QAM signal exhibits the PAs flexibility on optimizing efficiency and linearity.

A +27.3dBm transformer-based digital Doherty polar power amplifier fully integrated in bulk CMOS

This paper presents a digital Doherty polar power amplifier fully integrated in a 65 nm bulk CMOS process. It achieves +27.3 dBm peak output power and 32.5% peak PA drain efficiency at 3.82 GHz and 3.60 GHz, respectively. The PA demonstrates a maximum 7% back-off efficiency enhancement compared with a class-B PA and shows a robust Doherty PA operation against load variations. The 90° signal splitting at the Doherty input is realized by a compact folded transformer-based differential quadrature coupler. Active Doherty load modulation and output power combining are achieved by two transformers in a parallel configuration at the PA output. The transformer-based passive networks make the PA design ultra-compact (2.1 mm2) and broadband (24.9% for -1 dB bandwidth). Measurements with QPSK (1 MSym/s)/16QAM (0.5 MSym/s) signals show 3.5/4.7% rms EVM with +23.5/+22.1 dBm average output power and 26.8/24.1% PA drain efficiency.

2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement

Spectrum-efficient modulations in modern wireless systems often result in large peak-to-average power ratios (PAPRs) for the transmitted signals. Therefore, PA efficiency at deep power back-off (PBO) levels (e.g., -12dB) becomes critical to extend the mobiles battery life. Classic techniques, i.e., outphasing, envelope tracking, and Doherty PAs, offer marginal efficiency improvement at deep PBO in practice. Dual-mode PAs require switches at the PA output for high-/low-power mode selection [1,2], posing reliability and linearity challenges. Although simple supply switching (Class-G) is effective at deep PBO, it only offers Class-B-like PBO efficiency in each supply mode [3,4]. Multi-level outphasing PA requires multiple supplies and frequent supply switching [5], resulting in substantial DC-DC converter overhead and exacerbated switching noise.

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations

An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-/spl mu/m CMOS process. The phase noise lower than -90dBc/Hz at 100kHz offset is achieved over a wide tuning range (from 2.2GHz to 2.8GHz) under large process (/spl Delta/V/sub th/ = /spl plusmn/100mV), temperature (from /spl sim/35/spl deg/C to 85/spl deg/C), and power supply (from 1.8V to 3V) variations.

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique

This paper presents a broadband mixed-signal CMOS power amplifier (PA) with a hybrid Class-G Doherty architecture for PA efficiency enhancement up to the deep power back-off (PBO) region. Our proposed mixed-signal linearization technique ensures the PAs amplitude modulation (AM)-AM linearity by digital PA operation and suppresses the PAs AM-phase modulation (PM) nonlinearity by real-time analog phase compensation. The PA is fully integrated in a standard 65 nm bulk CMOS process, and achieves a peak output power (Pout ) of +26.7 dBm with a 40.2% peak drain efficiency (DE) at 3.71 GHz. The DE at 6 and 12 dB PBO is 1.8× and 2.6× over the reference Class-B PA operation, advancing the state-of-the-art CMOS PA PBO efficiency performance. The PA 1 dB bandwidth is extended from 1.08 to 1.8 GHz by reconfiguring the phase difference between the main and auxiliary paths in the Doherty PA. In the modulation measurements with 1 MSym/s 16 QAM signals, the PA performs dynamic hybrid Class-G Doherty operation and achieves +20.8 dBm peak Pout with 28.8% DE at 3.71 GHz and 2.42× efficiency enhancement at 8.1 dB PBO over Class-B operation. The real-time AM-PM linearization technique achieves 3.3 and 2.9 dB improvements on the EVM and adjacent channel leakage ratio (ACLR), respectively. The broadband Class-G Doherty operation is also demonstrated with modulated signals.