Shuai Sun

The Case for Hybrid Photonic Plasmonic Interconnects (HyPPIs): Low-Latency Energy-and-Area-Efficient On-Chip Interconnects

Moores law for traditional electric integrated circuits is facing increasingly more challenges in both physics and economics. Among those challenges is the fact that the bandwidth per compute on the chip is dropping, whereas the energy needed for data movement keeps rising. We benchmark various interconnect technologies, including electrical, photonic, and plasmonic options. We contrast them with hybrid photonic-plasmonic interconnect(s) [HyPPI(s)], where we consider plasmonics for active manipulation devices and photonics for passive propagation integrated circuit elements and further propose another novel hybrid link that utilizes an on-chip laser for intrinsic modulation, thus bypassing electrooptic modulation. Our analysis shows that such hybridization will overcome the shortcomings of both pure photonic and plasmonic links. Furthermore, it shows superiority in a variety of performance parameters such as point-to-point latency, energy efficiency, throughput, energy delay product, crosstalk coupling length, and bit flow density, which is a new metric that we defined to reveal the tradeoff between the footprint and performance. Our proposed HyPPIs show significantly superior performance compared with other links.

Fundamental Scaling Laws in Nanophotonics

The success of information technology has clearly demonstrated that miniaturization often leads to unprecedented performance, and unanticipated applications. This hypothesis of “smaller-is-better” has motivated optical engineers to build various nanophotonic devices, although an understanding leading to fundamental scaling behavior for this new class of devices is missing. Here we analyze scaling laws for optoelectronic devices operating at micro and nanometer length-scale. We show that optoelectronic device performance scales non-monotonically with device length due to the various device tradeoffs, and analyze how both optical and electrical constrains influence device power consumption and operating speed. Specifically, we investigate the direct influence of scaling on the performance of four classes of photonic devices, namely laser sources, electro-optic modulators, photodetectors, and all-optical switches based on three types of optical resonators; microring, Fabry-Perot cavity, and plasmonic metal nanoparticle. Results show that while microrings and Fabry-Perot cavities can outperform plasmonic cavities at larger length-scales, they stop working when the device length drops below 100 nanometers, due to insufficient functionality such as feedback (laser), index-modulation (modulator), absorption (detector) or field density (optical switch). Our results provide a detailed understanding of the limits of nanophotonics, towards establishing an opto-electronics roadmap, akin to the International Technology Roadmap for Semiconductors.

MorphoNoC: Exploring the design space of a configurable hybrid NoC using nanophotonics

Abstract As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0× or energy improvements of up to 1.37× over the base electronic network.

HyPPI NoC: Bringing Hybrid Plasmonics to an Opto-Electronic Network-on-Chip

As we move towards an era of hundreds of cores, the research community has witnessed the emergence of optoelectronic network on-chip designs based on nanophotonics, in order to achieve higher network throughput, lower latencies, and lower dynamic power. However, traditional nanophotonics options face limitations such as large device footprints compared with electronics, higher static power due to continuous laser operation, and an upper limit on achievable data rates due to large device capacitances. Nanoplasmonics is an emerging technology that has the potential for providing transformative gains on multiple metrics due to its potential to increase the light-matter interaction. In this paper, we propose and analyze a hybrid opto-electric NoC that incorporates Hybrid Plasmonics Photonics Interconnect (HyPPI), an optical interconnect that combines photonics with plasmonics. We explore various opto-electronic network hybridization options by augmenting a mesh network with HyPPI links, and compare them with the equivalent options afforded by conventional nanophotonics as well as pure electronics. Our design space exploration indicates that augmenting an electronic NoC with HyPPI gives a performance to cost ratio improvement of up to 1.8×. To further validate our estimates, we conduct trace based simulations using the NAS Parallel Benchmark suite. These benchmarks show latency improvements up to 1.64×, with negligible energy increase. We then further carry out performance and cost projections for fully optical NoCs, using HyPPI as well as conventional nanophotonics. These futuristic projections indicate that all-HyPPI NoCs would be two orders more energy efficient than electronics, and two orders more area efficient than all-photonic NoCs.

D 3 NoC: a dynamic data-driven hybrid photonic plasmonic NoC

It was previously shown that Hybrid Photonic Plasmonic Interconnect (HyPPI) is an efficient candidate for augmenting electronic network on chips (NoCs). Here we introduce a reconfigurable Hybrid Photonic Plasmonic NoC termed D3NOC, which intelligently augments electrical meshes with a hybrid photon-plasmon interconnect express bus. The intelligence uses the Dynamic Data Driven Application System (DDDAS) paradigm, where computations and measurements form a dynamic closed feedback loop. Our results show up to 67% latency improvements and 69% dynamic power net improvements beyond overhead-corrected performance compared to a 16 × 16 base electrical mesh.

Low-loss high-speed plasmonic optical modulator based on adiabatic waveguides

Here we proposed three adiabatically coupled waveguides (ACW), while the outer waveguides perform as a two-mode system analogous to ground- and excited- states and the middle waveguide is same as dark-state in a three-level-atomic system. Thanks to the dark-state, intermediate waveguide is based on plasmonic Indium thin oxide (ITO) as an active structure. Our simulation indicates a power consumption of 40 atto-joule with 50 dB modulation depth. In addition, our ACW plasmonic modulator provides high-speed operation as high as 5.4 THz and insertion loss as low as 0.45 dB. The proposed device is crucial for futuristic of optical short-reach interconnects.

Atto-Joule, high-speed, low-loss plasmonic modulator based on adiabatic coupled waveguides

Abstract In atomic multi-level systems, adiabatic elimination (AE) is a method used to minimize complicity of the system by eliminating irrelevant and strongly coupled levels by detuning them from one another. Such a three-level system, for instance, can be mapped onto physically in the form of a three-waveguide system. Actively detuning the coupling strength between the respective waveguide modes allows modulating light to propagate through the device, as proposed here. The outer waveguides act as an effective two-photonic-mode system similar to ground and excited states of a three-level atomic system, while the center waveguide is partially plasmonic. In AE regime, the amplitude of the middle waveguide oscillates much faster when compared to the outer waveguides leading to a vanishing field build up. As a result, the plasmonic intermediate waveguide becomes a “dark state,” hence nearly zero decibel insertion loss is expected with modulation depth (extinction ratio) exceeding 25 dB. Here, the modulation mechanism relies on switching this waveguide system from a critical coupling regime to AE condition via electrostatically tuning the free-carrier concentration and hence the optical index of a thin indium thin oxide (ITO) layer resides in the plasmonic center waveguide. This alters the effective coupling length and the phase mismatching condition thus modulating in each of its outer waveguides. Our results also promise a power consumption as low as 49.74aJ/bit. Besides, we expected a modulation speed of 160 GHz reaching to millimeter wave range applications. Such anticipated performance is a direct result of both the unity-strong tunability of the plasmonic optical mode in conjunction with utilizing ultra-sensitive modal coupling between the critically coupled and the AE regimes. When taken together, this new class of modulators paves the way for next generation both for energy and speed conscience optical short-reach communication such as those found in interconnects.

High Performance Photonic-Plasmonic Optical Router: A Non-blocking WDM Routing Device for Optical Networks

Here we show the first hybrid photonic-plasmonic, non-blocking, broadband router with 250 μm2 footprints, 480 GHz response time and 82 fJ/bit energy efficiency. The router supports multi-wavelengths over 200 nm at 70 Tbps data capacity.

Bit flow density (BFD): An effective performance FOM for optical on-chip interconnects

Here we propose a new figure of merit for optical on-chip links and networks named “Bit Flow Density”, which is a useful evaluation index that combines latency, throughput and footprint for precise crosstalk-based on-chip network design, simulation, and network simulators.

Low latency, area, and energy efficient Hybrid Photonic Plasmonic on-chip Interconnects (HyPPI)

In this paper we benchmark various interconnect technologies including electrical, photonic, and plasmonic options. We contrast them with hybridizations where we consider plasmonics for active manipulation devices, and photonics for passive propagation integrated circuit elements, and further propose another novel hybrid link that utilizes an on chip laser for intrinsic modulation thus bypassing electro-optic modulation. Link benchmarking proves that hybridization can overcome the shortcomings of both pure photonic and plasmonic links. We show superiority in a variety of performance parameters such as point-to-point latency, energy efficiency, capacity, ability to support wavelength division multiplexing, crosstalk coupling length, bit flow density and Capability-to-Latency-Energy-Area Ratio.