Shuhei Asada

Anomalous Seebeck coefficient observed in silicon nanowire micro thermoelectric generator

We have found experimentally an anomalous thermoelectric characteristic of an n-type Si nanowire micro thermoelectric generator (μTEG). The μTEG is fabricated on a silicon-on-insulator wafer by electron beam lithography and dry etching, and its surface is covered with a thermally grown silicon dioxide film. The observed thermoelectric current is opposite to what is expected from the Seebeck coefficient of n-type Si. The result is understandable by considering a potential barrier in the nanowire. Upon the application of the temperature gradient across the nanowire, the potential barrier impedes the diffusion of thermally activated majority carriers into the nanowire, and it rather stimulates the injection of thermally generated minority carriers. The most plausible origin of the potential barrier is negative charges trapped at the interface between the Si nanowire and the oxide film. We practically confirmed that the normal Seebeck coefficient of the n-type Si nanowire is recovered after the hydrogen forming gas annealing. This implies that the interface traps are diminished by the hydrogen termination of bonding defects. The present results show the importance of the surface inactivation treatment of μTEGs to suppress the potential barrier and unfavorable contribution of minority carriers.We have found experimentally an anomalous thermoelectric characteristic of an n-type Si nanowire micro thermoelectric generator (μTEG). The μTEG is fabricated on a silicon-on-insulator wafer by electron beam lithography and dry etching, and its surface is covered with a thermally grown silicon dioxide film. The observed thermoelectric current is opposite to what is expected from the Seebeck coefficient of n-type Si. The result is understandable by considering a potential barrier in the nanowire. Upon the application of the temperature gradient across the nanowire, the potential barrier impedes the diffusion of thermally activated majority carriers into the nanowire, and it rather stimulates the injection of thermally generated minority carriers. The most plausible origin of the potential barrier is negative charges trapped at the interface between the Si nanowire and the oxide film. We practically confirmed...

A scalable Si-based micro thermoelectric generator

A new device architecture of micro thermoelectric generator (μ-TEG) is proposed. The μ-TEG utilizes silicon nanowires as the thermoelectric (TE) material, and it can be fabricated by the CMOS-compatible process. It is driven by an “evanescent thermal field” exuding around a heat flow perpendicular to the substrate. We demonstrate experimentally that the TE power increases in the shorter TE leg lengths. The results show that the TE power density is scalable by miniaturizing and integrating the proposed structure.

Evaluation of controlled strain in silicon nanowire by UV Raman spectroscopy

The evaluation of strain states in silicon nanowires (Si NWs) is important not only for the surrounding gate field-effect transistors but also for the thermoelectric Si NW devices to optimize their electric and thermoelectric performance characteristics. The strain states in Si NWs formed by different oxidation processes were evaluated by UV Raman spectroscopy. We confirmed that a higher tensile strain was induced by the partial presence of a tetraethyl orthosilicate (TEOS) SiO2 layer prior to the thermal oxidation. Furthermore, in order to measure biaxial stress states in Si NWs accurately, we performed water-immersion Raman spectroscopy. It was confirmed that the anisotropic biaxial stresses in the Si NWs along the length and width directions were compressive and tensile states, respectively. The Si NW with a TEOS SiO2 layer on top had a larger strain than the Si NW surrounded only by thermal SiO2.

Enhanced nickelidation rate in silicon nanowires with interfacial lattice disorder

We demonstrate that the nickelidation (nickel silicidation) reaction rate of silicon nanowires (SiNWs) surrounded by a thermally grown silicon dioxide (SiO2) film is enhanced by post-oxidation annealing (POA). The SiNWs are fabricated by electron beam lithography, and some of the SiNWs are subjected to the POA process. The nickelidation reaction rate of the SiNWs is enhanced in the samples subjected to the POA treatment. Ultraviolet Raman spectroscopy measurements reveal that POA enhances compressive strain and lattice disorder in the SiNWs. By considering these experimental results in conjunction with our molecular dynamics simulation analysis, we conclude that the oxide-induced lattice disorder is the dominant origin of the increase in the nickelidation rate in smaller width SiNWs. This study sheds light on the pivotal role of lattice disorders in controlling metallic contact formation in SiNW devices.

ON current enhancement of nanowire Schottky barrier tunnel field effect transistors

Silicon nanowire Schottky barrier tunnel field effect transistors (NW-SBTFETs) are promising structures for high performance devices. In this study, we fabricated NW-SBTFETs to investigate the effect of nanowire structure on the device characteristics. The NW-SBTFETs were operated with a backgate bias, and the experimental results demonstrate that the ON current density is enhanced by narrowing the width of the nanowire. We confirmed using the Fowler–Nordheim plot that the drain current in the ON state mainly comprises the quantum tunneling component through the Schottky barrier. Comparison with a technology computer aided design (TCAD) simulation revealed that the enhancement is attributed to the electric field concentration at the corners of cross-section of the NW. The study findings suggest an effective approach to securing the ON current by Schottky barrier width modulation.