Shuichi Oka

8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS

High-performance systems require high-bandwidth interconnections. The aggregate bandwidth required between two processors, for example, is expected to extend into the terabit-per-second range or higher. Bandwidth is typically the bottleneck in such situations. Optical interconnect technologies have the potential to overcome bandwidth limitations for such chip-to-chip or board-to-board communication through increased channel speed and/or multiple channels. Channel speeds have reached 25 Gb/s and higher , in addition, a 24-channel transmitter and 24-channel receiver is disclosed that employs optical vias in silicon to couple the lens array. Two possible structures to implement a multichannel system are shown. A conventional multichannel architecture places the laser diode drivers (LDD) and VCSELs on the same side of the interposer. This paper describes a 12×5 two-dimensional optical I/O array for 600 Gb/s, utilizing 60 channels, each with an operating speed of 10Gb/s. The physical limitation in the number of channels is relaxed by connecting the LDDs through vias to the VCSELs placed on the opposite side of the interposer. The arrangement of the RX, in relation to the two-dimensional photo detector (PD) and TIA array, is the same as the TX. Key elements of each channel are the LDD consuming 2.17 mW/Gb/s and the TIA that consumes 0.96 mW/Gb/s while achieving an input-referred noise of 0.95 μArms. The low power of the LDD and TIA improve the package reliability while the high sensitivity of the TIA enables the transmission via a long optical waveguide.