Shunichi Ishiwata

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb system-in-silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mum CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm2 die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5 Gbps 64 Mb system-in-silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 m CMOS technology, the SoC core occupies 27.1 mm die area and consumes 1.41 W at 200MHz in typical work conditions.

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs

High-definition video applications, such as digital TV and digital video cameras, require high processing performance for high-quality visual images in addition to a complex video CODEC. Pre-/postprocessing to improve video quality is becoming much more important because requirements for pre-/postprocessing vary among applications and processing algorithms have not been stabilized. Therefore, a new processor architecture that has a highly parallel datapath is needed. In this paper, we introduce a VLIW vector media coprocessor, ldquovector coprocessor (VCP),rdquo that includes three asymmetric execution pipelines with cascaded SIMD ALUs. To improve performance efficiency, we reduce the area ratio of the control circuit while increasing the ratio of the arithmetic circuit. The total gate count of VCP is 1268 kgates and its maximum operating frequency is 300 MHz at 90-nm CMOS process. Some of the processing kernels in an adaptive prefilter that is applied to preprocessing for video encoding are evaluated. In the case of the edgeness and the sum of absolute differences, the performance is 183 giga operations per second. VCP offers enough performance for HD video processing and good cost-performance while all processing pipeline units operate effectively.

A single-chip MPEG-2 codec based on customizable media microprocessor

A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.

An H.264 full HD 60i double speed encoder IP supporting both MBAFF and Field-Pic structure

HD video sequences are widely used in todays multimedia systems and many of these are encoded with H.264 codec. However, it is still challenging to develop a high-performance H.264 encoder because the H.264 encoding process needs a large amount of computations and memory accesses. In this paper, a novel H.264 encoder is described. This encoder can encode video sequences of full HD 60i at double speed. Both MBAFF and Field-Pic structure are supported as coding tool for interlaced video sequences. The memory bandwidths are reduced by using a hierarchical motion estimation method and a pipeline configuration with consideration of MBAFF. The encoder is implemented with 1637K logic gates and 336.5KB on-chip SRAM in the 65nm CMOS technology.

Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding

The coexistence of MPEG-2 and its powerful successor H.264/AVC has created a huge need for MPEG-2/H.264 video transcoding. However, a traditional transcoder where an MPEG-2 decoder is simply cascaded to an H.264 encoder requires huge computational power due to the adoption of a complicated rate-distortion based mode decision process in H.264. This paper proposes a 2-D Sobel filter based motion vector domain method and a DCT domain method to measure macroblock complexity and realize content-based H.264 candidate mode decision. A new local edge based fast INTRA prediction mode decision method is also adopted to boost the encoding efficiency. Simulation results confirm that with the proposed methods the computational burden of a traditional transcoder can be reduced by 20% ∼ 30% with only a negligible bit-rate increase for a wide range of video sequences.

Side match distortion based adaptive error concealment order for 1Seg video broadcasting application

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation even becomes worse in 1Seg video broadcasting application, which is widely used in Japan and Brazil for mobile phone TV service, where errors are drastically increased and huge conjunctive areas inside a picture may be corrupted. In this case the error concealment order —to decide which MB should be concealed earlier —may highly influence image quality. Aimed this problem, this paper proposes an adaptive concealment order based on well-known Boundary Matching Algorithm (BMA). The concealment order is carefully chosen according to a lost MBs priority, which is formulated considering a concealed MBs side match distortion: an MB with smaller distortion should be concealed earlier compared with an MB with larger distortion. As for formulation of side match distortion, not only the current corrupted MBs, but also the neighboring MBs, which is caused by error propagation, are included. Compared with reference work [10], the experiments show our proposal achieves better performance of video recovery under different error rate channel in 1Seg application.

Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding

The coexistence of MPEG-2 and its powerful successor H.264/AVC has created a huge need for MPEG-2/H.264 video transcoding. This paper proposes a 2D Sobel filter based motion vector domain method and a DCT domain method to measure macroblock complexity and realize efficient H.264 candidate mode decision. A new local edge based fast INTRA prediction mode decision method is also adopted to boost the encoding efficiency. Simulation results confirm that with the proposed methods the computational burden of a traditional transcoder can be reduced by 20% ~ 30% with only a negligible bit-rate increase for a wide range of video sequences