Shunichi Toida

A note on Ádám's conjecture∗

Abstract It is shown that Adams conjecture is true for the following graphs: (1) nondirected cubic Cayley graphs; (2) nondirected quartic Cayley graphs with prime power vertices whose connection sets consist of units of congruence classes modulo the number of vertices.

Computational Complexity of Test-Point Insertions and Decompositions

We consider two basic computational problems that arise in the areas of pseudo-exhaustive testing, design, of polynomial-time testable classes, test-point inuertion, and Crosscheck, in the context of test generation and design for testability of combinational circuits. The first problem is to decom.pose a circuit info subcircuits such that the number of inputs to each subcircuit is bounded by I<; we show that this problem is NP-complete. This result establishes that the detection (minimization) problems associated with three polynomial-time testable classes and the method of pseudo-exhaustive testing are all NP-complete (hard). We then present simple approximation algorith.ms for solving these problems. The second problem deals with placing k test points on a circuit so as to facilitate the observability and/or controllability; this problem is also shown to be NP-hard. This problem arises in, the methods of Crosscheck and segment-cell placem.ent. 1 Tnt roduct ion There are several methods in the area of test generation and design for testability, and in these methods some basic computational problems appear in disguises in seemingly different contexts. We consider two such problems: circuit decompositions with bounded number of inputs for each subcircuit, and computing a subset of nets which can be used to inject and/or inspect signals. The first problem arises in the design of polynomial-time testable classes of combinational circuits [2,3,13], and in the method of pseudo-exhaustive testing [6,9,113. The second problem occurs in the method of segment cell placement [15] and in some parts of the method of CrossCIieck [16]. Despite the differences in the origins of their

Construction of quartic graphs

Abstract It is shown that all quartic graphs can be constructed successively from a K 5 by applying two types of operations called H -type and V -type expansions. It is also shown that the two types of operations are necessary to successively construct a regular graph of an even degree from a complete graph of the same degree.

Preposition senses: generalized disambiguation model

Our previous study on disambiguating the preposition “with” (using WordNet for hypernym and meronym relations, LCS for verb and preposition lexical information, and features of head and complement) looked promising enough to warrant study for other prepositions. Through investigation of ten frequently used prepositions, this paper describes general senses of prepositions and sense-case definitions, introduces a novel generalized sense disambiguation model, and demonstrates how this benefits a paraphrase recognition system.

Properties of a planar cubic graph

Abstract It is shown that a planar cubic graph can always be reduced to another planar cubic graph with fewer vertices. It is also shown that if a planar cubic graph is edge -3- colorable then the reduction of the number of its vertices is possible without changing colors of its edges.

On polynomial-time testable combinational circuits

The problems of identifying several nontrivial classes of Polynomial-Time Testable (PTT) circuits are shown to be NP-complete or harder. First, PTT classes obtained by using circuit decompositions proposed by Fujiwara (1988) and Chakradhar et al. (1990) are considered. Another type of decompositions, based on fanout-reconvergent (f-r) pairs, which also lead to PTT classes are proposed. The problems of obtaining these decompositions, and also some structurally similar general graph decompositions, are shown to be NP-complete or harder. Then, the problems of recognizing PTT classes formed by the Boolean formulae belonging to the weakly positive, weakly negative, bijunctive and affine classes are shown to be NP-complete. >

On polynomial-time testable classes of combinational circuits

The problem of test generation for detecting stuck-at faults in combinational circuits is computationally intractable. Consequently, the identification of classes of circuits that support polynomial-time test generation algorithms is very important from testing and design viewpoints. The authors discuss several classes of polynomially-time testable circuits. First, they consider the existing polynomial classes obtained by using decompositions of the circuits. Another type of decomposition is proposed, based on fanout-reconvergent pairs, which also lead to classes of polynomial-time testable circuits. Then, the authors present the classes of polynomial-time testable circuits that are formed by the Boolean formulae belonging to the classes of weakly positive, weakly negative, bijunctive and affine.<<ETX>>

Revisiting shift register realization for ease of test generation and testing

The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<<ETX>>

On test generation for combinational circuits consisting of AND and EXOR gates

Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.<<ETX>>