Shyh-Chyi Wong

Novel high positive and negative pumping circuits for low supply voltage

Novel charge pumping circuits for low supply voltages utilizing N-MOSFETs or P-MOSFETs with capacitors to generate positive and negative boosted voltages are presented. The two major factors limiting the pumping gain and efficiency are the body effect and the threshold voltage. Two techniques are proposed to minimize the influence of them. One is the new substrate connected technique to eliminate the body effect. The other one is the small pumping circuit providing higher gate voltages for the major pumping circuit to enhance pumping gain. With these two new techniques, the new pumping circuits have high positive and negative boosted voltages at low supply voltages.

A simple high-speed low current comparator

A high-speed low current comparator with low input impedance using a simple biasing method is proposed. Simulation results demonstrate the propagation delay is about 2.8 nsec and the average power consumption is 0.58 mW for 0.1 /spl mu/A input current at supply voltage of 3 V using 0.35 /spl mu/m CMOS technology.

An Analytical Delay Model for Read Operation at Any Position on Dyamic Random Access Memory Bit Lines

In deep submicron devices, the delay of interconnect becomes comparable to that of gate, which limits the circuit performance. Thus, it seems more appropriate to model the interconnect and the gate as a single component in study the device performance. Taking this approach, we develop an analytical model for the signal for a pre-charged, deep submicron dynamic random access memory (DRAM) at any position on the bit lines for read logic-1 operation. The bit line is modeled as a distributed resistance-capacitance (RC) line and is simultaneously solved with the drain current model. The model agrees well with the simulation program integrated circuits emphasis (SPICE) simulations using Berkeley short-channel IGFET model version 3 (BSIM3) models for various values of the bit line resistance, the capacitance on both the bit line and the sense amplifier, and the cell device width.

A delay model for DRAM bit lines with step and ramp word line signals

Abstract The read access time is a major performance index for DRAM products, on which the bit line delay is a critical factor. This delay is comparable to and tightly coupled with gate delay of both storage cell and sense amplifier, hence has to be solved as an integrated single component. In this paper, a voltage waveform and delay model of DRAM bit line for read logic-0 and logic-1 operation was developed. The bit line is modeled as a distributed resistance–capacitance line, and was solved based on simplified current models in both linear and saturation regions simultaneously. Our model shows good agreement with both SPICE and numerical device solvers, for both step and ramp word line signals as well as various bit line precharged levels. The new model significantly reduces the computation time to less than 1/200 that SPICE simulation requires.

A New Dual Floating Gate Flash Cell for Multilevel Operation

A new dual floating gate flash memory cell using constant bias voltages for multilevel operation is proposed to increase memory density. Channel hot electrons (CHE) and drain avalanche hot electrons (DAHE) are used to store different amounts of charge in different floating gates. To erase the data, channel fowler-nordheim (FN) tunneling is applied first, and then substrate hot electron (SHE) injection is utilized to prevent from over erase and tighten the threshold voltage spread. The simulation results indicate that the multilevel flash memory cell with slight modifications of triple well technology is a promising device for future multilevel operation devices.

Compact Expressions for Crosstalk of Multiple Bit Lines in DRAM

l.Introduction The crosstalk effect of two wires has been derived using distributed RC lines tll. The extension for three wires including inductance effect has also been proposed [2]. However, for the DRAM arrays, inclusion of the more accurate model of MOSFETs instead of simple resistance significantly enhances accuracy. The model of a DRAM cell with one distributed RC bit line has been derived for the MOSFET in saturation [3] and triode regions [4]. Since the distance between the bit lines tends to shrink and the cell number on the bit line.keeps increasing, accurate models of crosstalk help circuit designers design the sense amplifier and DRAM arrays. The compact expression combining accurate device models and distributed RC lines, as well as crosstalk of multiple bit lines for DRAM successfully predicts the waveforns on the bit line.