Sibum Kim

Interconnect Fabrication by Superconformal Iodine-Catalyzed Chemical Vapor Deposition of Copper

The mechanism behind superconformal filling of fine features during surfactant catalyzed chemical vapor deposition (CVD) is described and the metrology required to predict it is identified and quantified. The impact of adsorbed iodine coverage on copper deposition rate during chemical vapor deposition of copper on planar substrates is determined first. These kinetic parameters are then used in a model based on the curvature-enhanced accelerator coverage mechanism to predict superconformal filling during iodine-catalyzed CVD. In this model, the coverage of the adsorbed catalyst is presumed to change with surface area during interface evolution. The surface area decreases along the bottoms of submicrometer dimension features, increasing the local coverage and deposition rates and thereby enabling superconformal filling. Experimental filling results are then described and shown to be consistent with the predictions.

An Approach to the Development of Organic Additives for Electrodeposition of Narrow Copper Interconnects

We have characterized the electrochemical properties and wetting effects of various organic materials, including selected accelerators, suppressors, and wetters, for the electrodeposition of submicrometer-wide copper interconnects. An additive composition consisting of the following organic chemicals was tested: bis(3-sulfopropyl)-disulfide, disodium salt as an accelerator, polyethylene glycol as a suppressor, and a cross-linked polyamide as a second suppressor (working also as a wetter). Copper films plated using this makeup exhibited a surface roughness of ∼35 nm after annealing, with grain sizes on the order of 0.1-0.5 μm, and an electrical resistivity of ∼ 1.9 μΩ cm. Using this made-up solution, 120 nm wide trenches were successfully gap-filled.

3D Interconnect Process Integration and Characterization of Back Side Illuminated CMOS Image Sensor with 1.75 μm Pixels

The authors demonstrate process integration of a back side illuminated (BSI) 2 megapixel complementary metal oxide semiconductor (CMOS) sensor utilizing three-dimensional (3D) integration and wafer manufacturing operations with a silicon-on-insulator epi wafer. The manufacturing feasibility of a BSI CMOS image sensor is demonstrated and compared between the front side illuminated (FSI) and BSI versions of the sensor with the same fabrication process. The 3D integration processes are evaluated to obtain stable performance of the BSI CMOS image sensor. The broadband quantum efficiency (81% for BSI) is improved 2.7 times over FSI sensitivity. The dark current and other key pixel performance measures are compared against an equivalent conventional sensor. Simulations that predict the performance of a full-color sensor are discussed.

Effect of Acidity on Defectivity and Film Properties of Electroplated Copper Films

Decrease in acidity was very effective in reducing swirl defects. The occurrence of swirl defects in copper films plated with reduced acid electrolyte was reduced to less than one fifth of that plated with higher acid electrolyte, resulting in the huge decrease in the median defect count to less than one tenth. This reduction can be explained by more uniform plating on seed layers due to the higher resistance of the electrolyte. However, application of pretreatments did not further reduce swirl defects. Inspection on other postplating defects indicated that the major constituents for reduced and higher acid electrolytes were localized protrusions and embedded defects, respectively, and that fewer potential yield-killing defects were generated for reduced acid electrolyte. Analyses on film properties showed the highly Cu(111) texture, fine surface roughness, identical impurity levels, and complete fill of dual-damascene structure for both reduced and higher acid electrolytes. However, a significant degradation of via chain yield was observed for higher acid electrolyte, while no degradation was seen for reduced acid electrolyte. The overall analyses indicated that the use of reduced acid electrolyte led to improved defectivity performance and more reliable film properties compared to that of higher acid electrolyte.

Plasma Damage Mechanism of Electron Beam Curing Process for Spin on Dielectrics

This letter presents the plasma damage mechanism of electron beam curing process for spin on dielectrics. Device damage is studied using the antenna gate metal-oxide-semiconductor field-effect transistor (MOSFET) in terms of the threshold voltage variation as a function of electron beam conditions such as ambient and cathode voltage. Threshold voltages of nMOSFET are decreased by an electron beam curing process without antenna ratio dependency. The electron energy and interlayer dielectric thickness between active devices and metal layers largely affect the variation of threshold voltage. From the experimental results, it is concluded that device damage induced by an electron beam curing process is characterized as radiation damage rather than electron charging damage. For the damage free electron beam curing process, it is essential to control the penetration depth of high-energy electrons by adjusting the cathode voltage while considering the dielectric thickness over active devices.

Accelerated Superfilling Behavior and Suppressed Agglomeration of CEMOCVD Cu Film Using In Situ Plasma Treatment

We report the effect of preplasma treatment on the film planarity and superfilling properties of the chemically enhanced metal)organic chemical vapor deposition (CEMOCVD) Cu process. The void-free superfilling in a 50 nm technology scheme has made it the process of choice for copper-interconnect formation. There was dramatic improvement in homogeneity and planarity using dual-frequency preplasma treatment. The high frequency/low frequency = 50/500 W in situ dual-frequency plasma treatment prior to low-temperature deposition of CH 2 I 2 -treated CEMOCVD Cu film revealed improved planarity and homogeneous superfilling performance in 0.10 μm feature size.

Investigating the Planarization Behavior of High Selective Slurry with Initial Step Height and Pattern Density

The purpose of this study is to investigate the planarization behavior of high selective ceria slurry in terms of topography and pattern density variation. Planarization experiments have been performed using ceria slurry with various initial step heights and surrounding pattern density on active trench and shallow trench isolation. The threshold step height was measured in various layouts which showed different pattern density ranges, and the pattern density effect on the threshold step height has been discussed. The planarization capability of high selective slurry and the removal rate of the high density plasma oxide are strongly dependent on the whole chip topography rather than on the micropattern density.