Siddhartha Panda

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Anisotropic etching of polymer films by high energy (∼100s of eV) oxygen atom neutral beams

An inductively coupled high density plasma source was used to generate an energetic (100s of eV), high flux (equivalent of ∼10s mA/cm2) oxygen atom neutral beam. Positive ions were extracted from the plasma and neutralized by a metal grid with high aspect ratio holes. High rate (up to 0.6 μm/min), microloading-free, high aspect ratio (up to 5:1) etching of polymer with straight sidewalls of sub-0.25 μm features was demonstrated. The polymer etch rate increased with power and showed a shallow maximum with plasma gas pressure. The etch rate increased roughly as the square root of the boundary voltage (which controls neutral beam energy), and was independent of substrate temperature. The latter observation suggests that spontaneous etching did not occur. The degree of neutralization of the extracted ions was estimated to be greater than 99% at the base case conditions used in this work.

Effect of metastable oxygen molecules in high density power-modulated oxygen discharges

A spatially averaged (well mixed) reactor model was used to simulate a power-modulated (pulsed) high density oxygen discharge. Chemistry involving the high energy oxygen metastable molecules O2M(A 3Σu++C 3Δu+c 1Σu−) was included in the simulation. This chemistry was necessary to capture the experimentally observed increase in the O− negative ion density in the afterglow of the pulsed discharge. As the electron temperature drops in the afterglow, the rate coefficient of electron attachment with O2M increases several fold. The wall recombination probability of oxygen atoms affected the O− density drastically. For the conditions studied, the maximum O− density in the afterglow increased with pressure, decreased with power, and showed a maximum with pulse period. The time in the afterglow at which the peak O− density occurred decreased with pressure and power, and was independent of the pulse period. Knowing the temporal evolution of O− in the afterglow may be important for applications requiring extraction o...

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Design of high performance PFETs with strained si channel and laser anneal

The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond

Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.

Low temperature chemical vapor deposition of titanium nitride films from tetrakis(ethylmethylamido)titanium and ammonia

Abstract Titanium nitride films were deposited from tetrakis(ethylmethylamido)titanium and ammonia at 250–350°C and 0.7–2 Torr by thermal chemical vapor deposition. The effect of process parameters such as deposition temperature, precursor temperature, carrier gas flow, and ammonia flow on the film properties was studied, the apparent activation energy of film growth was calculated and the film composition was determined. The film step coverage was better than for films grown from tetrakis(dimethylamido)titanium and ammonia.

Etching high aspect ratio silicon trenches

Small ground rule ( 40) trenches in silicon are necessary to achieve required values of cell capacitance in the fabrication of charge-storage capacitors in dynamic random access memory devices. Etching of trenches suffers from a dynamic reactive ion etching (RIE) lag mechanism caused by constriction of trench openings during the etch process. Also, at high aspect ratios (accentuated by constriction of trench openings), reduced ion energy and etchant species flux to the trench bottom (etch front) results in slower etch rates leading to etch stop. This dynamic RIE lag effect and potential etch stop pose significant challenges towards obtaining deeper trenches. In this paper, two methods are proposed to minimize these problems. Short duration cleaning steps, predominantly etching in nature without any builtin deposition component, are used intermittently during the multistep etching sequence. Mask selectivity is preserved as these cleaning steps do not contribute significantly to the mask etch rate. The first method decreases the constriction of the trench opening by thinning the sidewall deposition, thus partially restoring the design dimension of the trench opening. The second method removes the etch-stop or blocking layer at the bottom of the trench without significantly contributing to sidewall thinning. These methods increase the differential etch rate of silicon at high aspect ratios, thereby help achieve the higher silicon depths required to meet the manufacturing process tool utilization targets.

Back-Channel Electrolyte-Gated a-IGZO Dual-Gate Thin-Film Transistor for Enhancement of pH Sensitivity Over Nernst Limit

A dual-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) was studied to obtain a pH sensitivity of ~160 mV/pH, which is above Nernst limit (59 mV/pH) with a low value of operating voltage (-5 to 5 V). The utilization of the active layer itself as the sensitive surface constitutes the dual-gate TFT structure with the back-channel gated with the electrolyte. The TFT characteristics were optimized by annealing the IGZO film in varying temperatures in oxygen ambience. A double-layered a-IGZO was used to sandwich the source/drain electrodes to eliminate the issues related with the high contact resistance and critical passivation of source/drain electrodes to protect from the exposure of the electrolyte. The single-gate electrolyte-gated thin film transistor showed the pH sensitivity of 24 mV/pH, which was enhanced by 6.7-fold by its dual-gate operation. The operation of dualgate TFT ion-sensitive field-effect transistors (ISFETs) with varying only bottom gate voltage eliminates the requirement of a reference electrode necessary in single-gate ISFETs. Such dual-gate ISFETs obviate the need of an additional high-K dielectric needed for the dual-gate TFT ISFETs and could also be fabricated on flexible substrates. These structures with the high sensitivity of ~160 mV/pH and requiring low (~2 μL) analyte solution could be the potential candidates for utilization as chemical and bio-sensors.